PROCESS DEVELOPMENT · CLEANROOM TRAVELER

Target CMOS · SOI with TiN gates

Six device-pattern levels · two spin-on dopants · self-aligned source/drain · one interconnect metal

This flow develops complementary transistors and simple integrated circuits on a thin, lightly doped SOI film. Boron and phosphorus spin-on sources form the p+ and n+ source/drain regions; a common TiN gate is chosen to avoid gate-doping steps and to investigate useful thresholds without well or channel implants.

It is the project’s target for a stocked-wafer, under-24-hour CMOS service. Mesa isolation, gate oxidation and blanket TiN deposition are performed in batches before orders arrive. The stock uses a fixed island grid; an order customizes gates, polarity selection, contacts and metal. Custom island geometry moves the mesa and gate-stack preparation back onto that order’s schedule.

The proposed baseline uses gate-first self-alignment, boron before phosphorus, and a fresh inorganic mask between the two dopants. Earlier masking oxides remain as part of the interlayer dielectric to conserve the gate oxide and buried oxide. This is a complete development traveler, not a qualified production recipe: its TiN/SOD compatibility, polarity blocking, contact process and repeatable turnaround still need measured release data.

Incoming SOI: 150 mm (100); 60 nm device Si starting target; lightly p-type, nominal ~10¹⁵ cm⁻³; 400 nm BOX target; actual thickness/doping and handle type recorded.
Stocked gate stack: Mesa-isolated device Si, approximately 50–55 nm after preparation; 15 nm thermal SiO₂; 50 nm TiN. All are proposed dimensions, not purchased tolerances.
Pattern levels: Campaign: MESA. Per order: GATE, PSELECT, NSELECT, CONTACT, METAL. Six total; five after the stock boundary. Passivation/PAD is an optional seventh level.
Mask / dielectric: Mask A: 200 nm dense PECVD SiO₂; mask B: another 200 nm; final ILD: 300 nm. Required blocking thickness and remaining-film limits come from the selected two-SOD cycle.
First circuit geometry: Gate L = 5 / 10 / 20 µm development ladder; initial CMOS Wp/Wn ≈ 3, then tune from measured drive. No 1 µm release is implied.
Deliverable: Electrically screened, diced, unpassivated bare research die. Packaging, environmental qualification and long-term reliability are outside this baseline.
Timing boundary: 24-hour objective starts when a qualified stock wafer and checked design are released to order processing; it includes processing, test, dicing and die inspection. No measured 24-hour result exists yet.

Lot / wafers ____________________Operator ____________________Date ____________________

Step explorer

Listed sequence ↓

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Section Drag to rotate · scroll to zoom Cut at section

Transfer / unchanged structure

No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.

3D process structure

NMOS · Along channel

PMOS · Along channel

Silicon body / handlen+ siliconp+ siliconThermal SiO₂ / BOXTiN gateDopant-block dielectricInterlayer dielectricPhotoresistBARC underlayerPhosphorus spin-on sourceBoron spin-on sourceAluminum metallization

Sections are cut from the same 3D material geometry. Film thickness, etch bias and diffusion lengths are exaggerated; coverage must be verified on the actual wafer.

Geometry and coverage

The cross-section cuts through two separate SOI islands, one n-channel and one p-channel. It shows material changes after each visit; thicknesses and lateral dimensions are exaggerated. Source/drain colors indicate intended electrically active regions. Diffusion tails, counterdoping, silicon consumption and TiN workfunction shifts are not predicted by the drawings. PSELECT opens the whole PMOS active area and its TiN gate landing/tab on BOX; NSELECT does the equivalent for NMOS. TiN defines the channel edge and stops the dielectric etch above gate/tab. Lateral diffusion and oxide undercut still change effective length. Mask A is retained after B. Mask B blankets and reseals the p+ regions before P. The final contact stack is intentionally unequal between polarities; the simplified picture does not replace the measured contact-depth map. The thin device films have no local body contact in this baseline. The SOI handle is a separate back-gate electrode if contacted; record its condition for every measurement. Doped S/D are drawn through the remaining SOI film as the intended target. The two-SOD profile/activation measurement must establish that condition; the illustration is not evidence of achieved junction depth. Morphology is illustrative rather than a dimensional prediction: directional plasma etches have steep walls, wet oxide etches retreat laterally, thermal oxidation consumes silicon, and deposited films follow their stated deposition method. Numerical geometry is deliberately exaggerated for legibility. Spin-on resist, BARC and dopant source films wet accessible relief and partially level it. Convex corners may be thin and recesses thick; a smooth drawing is the intended coverage, not evidence of pinhole-free coating. Wet, baked and thermally converted source states are distinguished. BOX isolates separate silicon islands; it does not prevent doping of an exposed mesa sidewall. After source/drain oxide clearing, SOD can contact those sidewalls and supply dopant inward. Only the channel segment retains the intended oxide/gate wrap, subject to continuity, lateral etch retreat and diffusion limits. Use the transverse channel section to inspect the gate/oxide wrap and the transverse source/drain section to see exposed mesa faces. The longitudinal section alone hides the channel-side edges. At the channel, the gate mask encloses the complete film wrap on both mesa sidewalls and extends onto BOX on both sides. The contact tab is intentionally one-sided; protective enclosure is required at both edges. No enclosure dimension can be read from this exaggerated drawing.

Campaign · isolate the SOI islands

C001 · Receive and identify SOI

Record the front/back condition, flat, supplier lot and wafer identity. Load matched SOI monitor wafers plus oxide and TiN blanket witnesses.

Go to this visit in the run sheet ↓

Lot recipe assignments

Use these assignments wherever their IDs appear in the sequence. Complete the values before starting the affected module.

Assignment	Value for this lot	Context
C-STACK Stock wafer and isolation	MESA etch recipe/revision ____; dry gate-oxide growth time ____; measured Si/BOX/oxide/TiN thickness maps ____; fixed island-grid revision ____	Initial 60 nm Si becomes thinner during sacrificial/gate oxidation and later SOD. A 400 nm BOX is a proposed etch budget, not immunity to HF. Freeze the actual incoming stack and minimum remaining Si/BOX before devices start.
C-TIN TiN gate module	Deposition tool/recipe ____; gate etch tool/recipe ____; etch selectivity/undercut ____; complete two-SOD stack-test ID ____	MRC944 lists a TiN target; Centura-MET permits TiN and is the gate-etch candidate. Deposition power/rate and thin-gate-oxide etch selectivity still require current calibration. A successful AIST TiN/SOD circuit precedent does not establish gate-first TiN survival here. No automatic peroxide clean, piranha, or oxygen ash on exposed TiN.
C-ROUTE Material-history route	TiN+source-present RTA tool ____; wet benches ____; oxide etcher ____; resist strip/dechlorination ____; return-from-probe cleaning ____	After TiN or SOD, do not return to MOS-clean furnaces or no-metal etchers. RTP3 is a candidate only after acceptance of exact SOD chemistries plus TiN; its published list does not establish either. It explicitly bars MSINK6/MSINK8 acid exposure for metal wafers. A visit to general MSINK16/18 also bars return to MSINK1/6/7/8; bind the whole wet route. Centura-MxP is prohibited for TiN-bearing wafers.
C-LITHO Lithography	Dose per surface/mask ____; alignment mode ____; minimum enclosure ____; final resist thickness/CD limits ____	MiR701 track reference is 2 µm, 90°C/90 s soft bake, 110°C/90 s PEB and MF-26A/60 s develop. MLA150 dose is calibrated separately on SOI, TiN, mask oxide and Al–Si. These track values are references, not a substitute for film-specific pattern qualification.
C-MASK Two polarity masks and oxide etches	Dense oxide recipe ____; A/B initial and minimum remaining thickness ____; SOD-glass strip rates ____; BOX/gate-edge losses ____; wet-window recipe ____	200 nm A and 200 nm B are proposed starting dimensions. Demonstrate blocking of B and P through the complete cumulative thermal history. Strip source glass selectively while retaining masks; do not blanket-remove A or B. NSELECT must clear measured A+B+gate oxide; PSELECT clears A+gate oxide.
C-B Boron SOD	Product/lot ____; coat rpm/time ____; cure temperature/time ____; B diffusion T/time/ambient/ramp ____; boron-rich-layer treatment ____; glass strip ____	Use a source-specific module. The AIST paper identifies boron-glass removal and silicon consumption; it does not supply a released NanoLab/TiN recipe. Any oxidizing residue treatment must pass the TiN stack test. Never copy an unrelated 950°C/4 min recipe into an RTP dwell envelope.
C-P Phosphorus SOD	Product/lot ____; coat rpm/time ____; cure temperature/time ____; P diffusion T/time/ambient/ramp ____; glass strip ____	B-first is the chosen development sequence so p+ monitors see the subsequent P cycle. Freeze it only after measurements of both polarities, lateral diffusion, compensation, residual Si and threshold shift. Spin speeds and 950°C/30–60 s values from older NMOS drafts are not validated CMOS values.
C-CONTACT Unequal-depth contact openings	Wet oxide contact etch ____; oxide/TiN/Si rates ____; n/p clear times ____; TiN-loss allowance ____; residual oxide removal ____	PSELECT/NSELECT include same-polarity gate tabs, giving nominal p-S/D and p-gate B+ILD (~500 nm) versus n-S/D and n-gate ILD (~300 nm). Verify location-specific thicknesses. One mask is allowed only if early-clearing Si and TiN survive until the deepest contact clears. Otherwise redesign with separate contact masks. SEMI is a case-reviewed plasma-etch candidate, not a substitute for measured selectivity.
C-METAL Contacts and metallization	Pre-metal clean/ion dose ____; MRC944 permitted power and rate ____; BARC film/cure and masked-open recipe ____; Al–Si etch/corrosion clean ____; contact TLM limits ____; optional anneal ____	500 nm Al–2%Si is the target; as-deposited contact performance is measured first. No anneal is required by this baseline. A sinter must be independently released against thin-SOI consumption/spiking and both p+/n+ contact resistance; a generic 400°C recipe is not automatically safe.
C-TEST Electrical and shipment specification	Operating VDD ____; handle/back-gate condition ____; Vt/Ioff/Ig/contact/isolation limits ____; wafer sampling and die test ____; dicing recipe ____	The handle is not the SOI body. Keep its electrical condition reproducible and record any verified handle contact. No grounded-body claim comes from a chuck. Release thresholds and supply only from measured devices; test results at one floating-handle condition do not qualify all packaging conditions.

Cleanroom sequence

87 visits

Each numbered visit follows the wafer to a tool, bench or measurement station. The section at right shows the intended structure after that visit.

Campaign · isolate the SOI islands

BATCH PREPARATION

These visits prepare stock independently of customer orders. A fixed mesa grid and alignment system are part of the stock specification.

Visit / destination	Operation, settings and check	Wafer after this visit
C001Receive and identify SOIInspection microscope□ Done __________	Record the front/back condition, flat, supplier lot and wafer identity. Load matched SOI monitor wafers plus oxide and TiN blanket witnesses. Proposed starting film 60 nm lightly p-type Si; 400 nm BOX Format 150 mm (100), compatible flat/thickness/bow Check No edge damage, backside particles or unsupported stack substitution. Record Wafer and witness IDs index	NMOS · Along channel PMOS · Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
C002Map incoming SOIEllips2 / NanoDUV□ Done __________	Fit Si/BOX/handle together using the supplier stack. Record device-film and BOX maps before any etch or oxidation. Sampling Center + four radial sites minimum Electrical background Supplier certificate plus qualified monitor measurement; ~10¹⁵ cm⁻³ is a target Check Film model fits; establish C-STACK minimum residual thicknesses. Record Thickness map and fit residual index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C003Clean incoming SOIMSINK6 accepted MOS clean□ Done __________	Use the current incoming-wafer MOS clean and complete its rinse/dry route. Native-oxide removal is allowed here only within the SOI/BOX budget. Recipe Current MSINK6 sequence, bath identities and times logged Check No metal history; no uncontrolled HF exposure of BOX. Record Clean completion and transfer time wet6	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C004Coat MESA resistSVGCOAT6 or accepted metal-compatible manual route□ Done __________	Coat the wafer with the selected positive MiR701 program; complete its bake and cool within this visit. Reference film 2 µm MiR701; 90°C / 90 s soft bake Program C-LITHO; no incompatible prime or strip chemistry Check Continuous film at mesa/gate steps; back and bevel clean. Record Recipe and film witness coat · morph-spin	NMOS · Along channel PMOS · Along channel Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
C005Expose MESAMLA150□ Done __________	Align and expose the released MESA pattern at its stack-specific dose. Keep the common origin and use at least two separated alignment marks. Wavelength 375 nm Dose and focus C-LITHO; measured on this film stack Check Both marks acquired; correct tone and device polarity. Record Dose, focus, alignment residual mla	NMOS · Along channel PMOS · Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
C006Develop MESASVGDEV6 / accepted developer route□ Done __________	Complete PEB, development, rinse and dry as one track visit. Reference PEB 110°C / 90 s Reference development MF-26A / 60 s; calibrated endpoint Check Openings clear without attacking unprotected device silicon. Record Program; develop time develop	NMOS · Along channel PMOS · Along channel Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
C007Inspect MESAOptical microscope / linewidth tool□ Done __________	Measure opening/gate CDs and overlay at center and edge; reject bridges or pinholes. Locations At least center and four radial sites Record CD and overlay against released enclosure limits Check No residual resist at intended openings; wrong polarity stops the wafer. Record Images and CDs index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C008Etch isolation to BOXLAM8 or accepted Si etcher□ Done __________	Clear exposed device silicon and stop on the buried oxide. Preserve isolated n/p device islands and alignment marks. Depth Measured ~60 nm device film Recipe C-STACK; silicon endpoint plus calibrated minimum overetch Check No silicon stringers connecting islands; BOX not perforated. Record Etch trace, depth and witness loss lam8 · morph-etch	NMOS · Across mesa · source PMOS · Across mesa · source Directional plasma mesa etch Directional Si etching clears the gaps to BOX and leaves approximately vertical mesa walls. BOX electrically separates islands; it does not protect a later-exposed sidewall against dopant diffusion.
C009Strip mesa resistAccepted pre-metal resist strip / asher□ Done __________	Remove resist and etch residue before the MOS clean. This is the last stage where a standard oxygen-ash route may be selected without exposed TiN. Strip Complete removal; recipe bound to incoming SOI history Check Clean mesa edges; no visible carbon residue. Record Strip recipe index	NMOS · Across mesa · source PMOS · Across mesa · source Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
C010Inspect isolation and edge profileOptical microscope / step metrology□ Done __________	Measure island dimensions and etch depth; inspect narrow gaps and mesa corners. Use a sacrificial monitor for higher-resolution inspection if necessary. Isolation checks Continuous etched gaps down to BOX; no re-entrant fences Check Accept isolation geometrically before oxidation. Record Mesa map and edge images index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C011Preclean processed SOI before MOS cleanMSINK8 accepted pre-furnace organic clean□ Done __________	Clean the previously patterned wafer immediately before its MSINK6 visit, using the accepted pre-metal route. Complete the rinse/dry/transfer program and count any allowed oxide-removal loss. History Mesa resist/etch processing makes this a processed wafer Recipe Current MSINK8 pre-furnace clean; no TiN has been deposited Check No residual organics; wafer is eligible for MSINK6. Record Tool recipe, actual settings and completion time wet8 · wet6	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C012Clean before gate oxidationMSINK6□ Done __________	Perform the accepted final MOS clean with oxide removal budgeted. Rinse/dry and move directly to oxidation using the prescribed clean carrier. Queue Record clean-to-furnace time HF Only the bounded pre-oxide step; measure exposed-BOX loss Check No organics or incompatible history. Record Bath and queue record wet6	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.

Campaign · form and stock the gate stack

BATCH PREPARATION

All MOS furnace work finishes before TiN deposition. Thermal oxide covers exposed mesa tops and sidewalls; the sputtered TiN channel-side wrap must be demonstrated continuous before relying on it during wet clears and SOD.

Visit / destination	Operation, settings and check	Wafer after this visit
C013Grow thermal gate dielectricTystar1 · 1GATEOXA□ Done __________	Grow gate-quality dry oxide and complete the accepted in-tube anneal/cooldown. Include a matching bulk oxide monitor and SOI optical monitor. Target 15 nm thermal SiO₂; proposed Temperature 1000°C development target, subject to loaded recipe Time / anneal C-STACK; calibrated growth time and full thermal trace Check Keep Si consumption in the total budget; no TiN or SOD has entered this tube. Record Thermal trace and load map oxide · morph-fab	NMOS · Across mesa · gate PMOS · Across mesa · gate Thermal oxidation / silicon consumption Thermal oxide consumes exposed Si on mesa tops and sides while expanding outward. It does not deposit a new layer on exposed BOX. Nominal 15 nm oxide consumes about 6.6 nm Si; local corner thickness is schematic.
C014Measure oxide and remaining SiEllips2 / NanoDUV□ Done __________	Map oxide and SOI film on witnesses; inspect for particles and watermarks. Record actual remaining Si rather than assuming it equals the initial film minus a nominal calculation. Expected scale ~50–55 nm remaining Si for this proposed starting stack Oxide target 15 nm, actual mean/range recorded Check No unexplained thickness or fit variation. Record Oxide/Si/BOX map index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C015Deposit TiN gate filmMRC944 TiN target or released TiN deposition tool□ Done __________	Deposit the bound TiN recipe on the clean thermal oxide. Preserve the gate dielectric; no blanket pre-sputter that removes oxide is permitted. Target 50 nm TiN Recipe C-TIN: stoichiometry, power/gas, pressure, temperature and rate Check Conductive TiN on horizontal surfaces and demonstrated continuity/minimum coverage on channel-side mesa walls. Top-film sheet resistance alone does not establish a continuous sidewall gate. Record Deposition log and witness ID sputter · materials · morph-deposit	NMOS · Across mesa · gate PMOS · Across mesa · gate Sputtered TiN / limited sidewall coverage Sputtered TiN coats the top more strongly than steep sidewalls. The thinner sidewall film shows the intended gate wrap; its continuity on the actual mesa profile must be established before it can protect the channel edge.
C016Measure TiN filmFour-point probe / thickness / stress metrology□ Done __________	Measure thickness and sheet resistance on a blanket witness. Record stress/bow and use independent capacitors to track effective workfunction/flat-band behavior. The MOS-capacitor witness requires a verified substrate/body reference; a chuck alone is not a valid C–V body terminal. Witness Dedicated TiN-on-oxide; do not pierce a device gate oxide Check Film passes C-TIN limits and full-cycle stack qualification. Record Thickness, sheet resistance and C–V baseline hu	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C017Place qualified stock in clean storageClean cassette / sealed wafer box□ Done __________	Return the accepted stack to its identified clean carrier. Log storage conditions and the exact fixed-island layout revision. Stock boundary Mesa + thermal oxide + blanket TiN complete Label Full TiN process history; no MOS-clean return Check Only qualified stock is available for timed customer runs. Record Stock lot, location, timestamp materials	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.

Order · pattern the self-aligned TiN gates

CUSTOMER-ORDER PROCESS

Five custom pattern levels begin here. The 24-hour target includes every remaining visit; it has not been timed or demonstrated.

Visit / destination	Operation, settings and check	Wafer after this visit
C018Retrieve and inspect stockInspection microscope□ Done __________	Retrieve the assigned stock wafer and verify island-grid/design compatibility. Inspect the exposed TiN for contamination before coating. Clock Log order start and wafer removal time Check Correct stock revision; gate patterns fit available islands. Record Start time; wafer condition index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C019Clean the TiN surfaceC-ROUTE metal-compatible wet bench□ Done __________	Use the released non-destructive surface clean for stored TiN. No unqualified peroxide, piranha or blanket HF is used. Recipe C-TIN / C-ROUTE Check No corrosion, discoloration or excessive TiN resistance change. Record Clean recipe and queue index	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C020Coat GATE resistSVGCOAT6 or accepted metal-compatible manual route□ Done __________	Coat the wafer with the selected positive MiR701 program; complete its bake and cool within this visit. Reference film 2 µm MiR701; 90°C / 90 s soft bake Program C-LITHO; no incompatible prime or strip chemistry Check Continuous film at mesa/gate steps; back and bevel clean. Record Recipe and film witness coat · morph-spin	NMOS · Across mesa · gate PMOS · Across mesa · gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
C021Expose GATEMLA150□ Done __________	Align and expose the released GATE pattern at its stack-specific dose. Keep the common origin and use at least two separated alignment marks. Wavelength 375 nm Dose and focus C-LITHO; measured on this film stack Check Both marks acquired; correct tone and device polarity. Record Dose, focus, alignment residual mla	NMOS · Along channel PMOS · Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
C022Develop GATESVGDEV6 / accepted developer route□ Done __________	Complete PEB, development, rinse and dry as one track visit. Reference PEB 110°C / 90 s Reference development MF-26A / 60 s; calibrated endpoint Check Openings clear without attacking unprotected device silicon. Record Program; develop time develop	NMOS · Across mesa · source PMOS · Across mesa · source Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
C023Inspect GATEOptical microscope / linewidth tool□ Done __________	Measure gate length/width and verify gate-mask enclosure beyond both mesa sidewalls onto BOX. The one-sided contact tab does not replace the required enclosure on the opposite side. Reject any route around a gate at a mesa edge. Locations At least center and four radial sites Record CD and overlay against released enclosure limits Check No residual resist at intended openings; wrong polarity stops the wafer. Record Images and CDs index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C024Etch TiN gatesCentura-MET or released TiN etcher□ Done __________	Clear TiN outside gate lines and landings, stopping on thermal oxide. Keep the thermal oxide over source/drain silicon for subsequent resist processing. Film 50 nm TiN nominal Endpoint / overetch C-TIN; oxide-loss and edge-bias limits Check Intended TiN gate wrap survives on both channel-side mesa walls; no unwanted TiN stringers remain around S/D mesa feet or between gates. Record Etch trace and measured bias tinet · morph-etch	NMOS · Across mesa · gate PMOS · Across mesa · gate Directional plasma TiN etch The plasma etch defines the gate but may leave TiN fences at mesa feet. These are unwanted residues, not protective channel material; inspect the stepped witness before accepting the cleared profile.
C025Strip gate resist and remove etch residueC-ROUTE strip / dechlorination bench□ Done __________	Complete the TiN-qualified strip and residue clean. Any plasma/oxidizing step must be part of the tested TiN module. Recipe C-TIN; no default Matrix oxygen ash on exposed TiN Check No conductive residue or polymer remaining; oxide still covers exposed S/D. Record Strip/dechlorination recipe index	NMOS · Across mesa · source PMOS · Across mesa · source Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
C026Inspect gates and film retentionOptical microscope / witness metrology□ Done __________	Inspect gate continuity, gate-edge geometry and isolation at mesa corners. Measure residual oxide/TiN on the appropriate witness. Critical control Gate-edge oxide and TiN survival Check Gate cuts clear; sidewall fences absent. Record CDs, oxide loss and images index · morph-deposit · morph-etch	NMOS · Across mesa · gate PMOS · Across mesa · gate Gate / sidewall inspection Check TiN gate continuity and confirm that the bound etch cleared unwanted fences outside the intended gate footprint. The subsequent nominal picture assumes this inspection passes; sputtered channel-side coverage remains a measured requirement.

Order · boron-selective p+ source/drain

CUSTOMER-ORDER PROCESS

Mask A blocks boron from NMOS islands. The PSELECT level refers to p-type device selection, not phosphorus. TiN remains exposed over the selected PMOS gate during the SOD module.

Visit / destination	Operation, settings and check	Wafer after this visit
C027Deposit polarity mask AOxford PECVD4 or C-MASK chamber□ Done __________	Deposit the qualified dense oxide blocker on all islands and gates. This film is retained after the boron cycle. Target 200 nm SiO₂ Reference chamber temperature 350°C; use C-MASK recipe and measured rate Check Film continuous over gate edges; blocking data cover the selected B cycle. Record Thickness witness and recipe pecvd · morph-deposit	NMOS · Across mesa · gate PMOS · Across mesa · gate PECVD / finite step coverage PECVD covers tops, steps and sidewalls with finite, recipe-dependent step coverage. Rounded contours show intended insulation; pinholes, seams and thin corners require witness checks.
C028Measure mask AEllips2 / NanoDUV□ Done __________	Measure oxide thickness and nonuniformity on a witness. Use optical inspection to check for pinholes or cracks at gate topography. Acceptance Minimum local thickness from C-MASK, not merely 200 nm average Check No under-thickness region relative to blocker criterion. Record Thickness map index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C029Coat PSELECT resistSVGCOAT6 or accepted metal-compatible manual route□ Done __________	Coat the wafer with the selected positive MiR701 program; complete its bake and cool within this visit. Reference film 2 µm MiR701; 90°C / 90 s soft bake Program C-LITHO; no incompatible prime or strip chemistry Check Continuous film at mesa/gate steps; back and bevel clean. Record Recipe and film witness coat · morph-spin	NMOS · Across mesa · gate PMOS · Across mesa · gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
C030Expose PSELECTMLA150□ Done __________	Align and expose the released PSELECT pattern at its stack-specific dose. Keep the common origin and use at least two separated alignment marks. Wavelength 375 nm Dose and focus C-LITHO; measured on this film stack Check Both marks acquired; correct tone and device polarity. Record Dose, focus, alignment residual mla	NMOS · Along channel PMOS · Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
C031Develop PSELECTSVGDEV6 / accepted developer route□ Done __________	Complete PEB, development, rinse and dry as one track visit. Reference PEB 110°C / 90 s Reference development MF-26A / 60 s; calibrated endpoint Check Openings clear without attacking unprotected device silicon. Record Program; develop time develop	NMOS · Across mesa · source PMOS · Across mesa · source Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
C032Inspect PSELECTOptical microscope / linewidth tool□ Done __________	Confirm PMOS islands are selected and NMOS islands are fully covered. Selection windows include PMOS gate tops; their edges lie beyond active mesas with measured enclosure. Include the complete same-polarity TiN gate landing/tab in the selected region so mask A is removed above it. Locations At least center and four radial sites Record CD and overlay against released enclosure limits Check No residual resist at intended openings; wrong polarity stops the wafer. Record Images and CDs index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C033Open PMOS diffusion windowsC-MASK metal-compatible oxide etch bench□ Done __________	Etch mask A plus exposed 15 nm gate oxide in the selected PMOS regions. TiN remains as the channel-defining hard mask. Complete rinse/dry. The selection includes the PMOS TiN landing/tab on BOX as well as its active mesa. The etch removes A above that TiN while preserving its underlying dielectric. Clear thickness Measured A + gate oxide on S/D; TiN shields underlying channel oxide only where continuous, while wet etchant can retreat laterally at accessible edges BOX / gate edge Account for BOX recession and lateral oxide retreat Check S/D silicon clears; NMOS mask remains intact; gate oxide is not excessively undercut. Record Clear time, oxide-loss witness wetmetal · morph-etch	NMOS · Across mesa · source PMOS · Across mesa · source Isotropic wet polarity-window etch Wet etching opens PMOS S/D tops and sidewalls, retreats under mask/gate edges and recesses accessible BOX. NMOS remains sealed by its blocking oxide, including its sidewalls. TiN only shields channel oxide where its coverage remains continuous.
C034Remove PSELECT resistC-ROUTE TiN-compatible strip□ Done __________	Strip resist completely without removing the boron blocker. Clean residue using the released sequence. Thermal condition No resist, tape or organic residue may enter the SOD diffusion cycle Check Open p-S/D clean; no TiN corrosion. Record Strip result index	NMOS · Across mesa · source PMOS · Across mesa · source Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
C035Clean exposed p-source/drain surfacesC-ROUTE bounded pre-SOD clean□ Done __________	Remove native/contact oxide only by the released short clean and load promptly into coating. Preserve mask A, gate edges and BOX. Complete the designated DI rinse and dry before SOD coating; carry no liquid acid into the spinner. Oxide budget Log oxide loss and queue to coat Check Bare exposed silicon; blocker and gate dielectric pass minimums. Record Clean time and queue index	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C036Coat boron sourceDedicated accepted SOD spinner / Headway route□ Done __________	Dispense and spin the exact boron source over device and corresponding B-only/B-then-P witnesses. Inspect bevel/backside and remove prohibited contamination by the bound procedure. Product / spin C-B; bottle identity, age, dispense, rpm and seconds Check Continuous source on intended PMOS top/side faces; check wetting and corner minima. Carrier and backside meet thermal-tool rules. Record Bottle lot and coating log headway · morph-spin	NMOS · Across mesa · source PMOS · Across mesa · source Spin coating / wet boron source The wet spin-on source reaches accessible tops and sidewalls and can gather at low corners. Its partly leveled profile is illustrative; actual wetting and corner thickness depend on the selected formulation. The exposed PMOS S/D faces receive source; the other polarity and channel edges depend on continuous blocking/gate coverage.
C037Cure boron sourceDedicated SOD hotplate□ Done __________	Cure the source using the product-specific recipe and transfer in the accepted carrier. Temperature / time C-B; actual hotplate temperature and timer Check No cracking or uncured volatile residue. Record Cure and transfer time index	NMOS · Along channel PMOS · Along channel Source cure / dry precursor The cure removes solvent and converts the wet source into the specified dry precursor. Some shrinkage and profile change are expected; the retained coating is not a second deposited layer.
C038Diffuse / activate p+ source and drainC-ROUTE accepted TiN + SOD thermal tool□ Done __________	Run the boron thermal module on devices and the complete witness set. Include a boron-residue oxidation segment only if it is qualified with TiN and lies within the tool envelope. Peak / dwell / ramp / gas C-B; full logged recipe No assumed recipe Source-present TiN acceptance and temperature calibration are explicit bindings Check No TiN stack failure; thermal trace inside the released window. Record Trace, load map and emissivity/calibration rtp · aist · morph-fab	NMOS · Across mesa · source PMOS · Across mesa · source Boron diffusion from exposed faces Dopant enters exposed silicon in contact with the source and spreads laterally as well as inward. The remaining source is converted glass; colored silicon is a qualitative doped volume, not a concentration contour. PMOS sidewalls are deliberately doped where exposed; NMOS remains under mask A. The depicted through-film target must be confirmed by profile measurements.
C039Remove boron glass and residueC-ROUTE source-glass wet bench□ Done __________	Remove the boron glass using the selected source-specific process. Retain mask A over NMOS; do not blanket-strip its remaining oxide. Recipe / end point C-B; no unqualified oxidizing cleanup on TiN Loss limits Gate edge, TiN and BOX; mask-A residual minimum Check No boron-rich interfacial residue; all protected regions still have blocking oxide. Record Strip time, residue images and loss aist · wetmetal · morph-fab	NMOS · Across mesa · source PMOS · Across mesa · source Source-glass removal The source glass is removed while the doped silicon remains. Accessible gate-edge oxide, masking oxide and exposed BOX may also recede according to the source-specific strip; the final loss requires measurement.
C040Measure post-boron witnessesMetrology / isolated sheet-resistance station□ Done __________	Measure active p+ sheet resistance on isolated SOI monitors, remaining silicon, mask thickness and TiN sheet resistance. Keep product gates unprobed before later deposition. Monitors B-only and B-then-P duplicates; masked n-region control Doping Electrical activation plus profile monitor; sheet resistance alone does not prove depth Check B module passes before resealing p+ regions. Record Resistance, thickness and dopant-profile reference index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Order · reseal p+ and form n+ source/drain

CUSTOMER-ORDER PROCESS

A fresh mask B covers the entire wafer before phosphorus. PMOS p+ regions stay sealed during the P cycle; previously opened windows are never assumed to protect themselves.

Visit / destination	Operation, settings and check	Wafer after this visit
C041Clean for the second blockerC-ROUTE accepted pre-PECVD clean□ Done __________	Remove residues with the TiN/SOD-compatible cleaning module. Preserve the retained mask A and protect the cleaned exposed PMOS silicon until deposition. Queue C-MASK clean-to-deposition limit Check No source glass or organic residue enters PECVD. Record Clean and queue index	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C042Deposit polarity mask BOxford PECVD4 or C-MASK chamber□ Done __________	Blanket-deposit fresh dense oxide over TiN, p+ source/drain and remaining mask A. This reseals the entire PMOS island. Target 200 nm additional SiO₂ Reference temperature 350°C; C-MASK recipe Check Measured minimum B coverage on PMOS tops, corners and sidewalls blocks the complete P cycle. Record Deposition and witness pecvd · morph-deposit	NMOS · Across mesa · gate PMOS · Across mesa · gate PECVD reseal / finite step coverage PECVD covers tops, steps and sidewalls with finite, recipe-dependent step coverage. Rounded contours show intended insulation; pinholes, seams and thin corners require witness checks. Mask B must reseal PMOS S/D sidewalls as well as their tops before phosphorus is coated.
C043Measure the resealEllips2 / NanoDUV / microscope□ Done __________	Measure mask B on open-Si and retained-A witnesses; check seams and pinholes over PMOS gate edges. Stacks PMOS: B; NMOS: residual A + B, over pre-existing gate oxide Check No exposed p+ silicon; depth map complete for NSELECT. Record Local thickness map index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C044Coat NSELECT resistSVGCOAT6 or accepted metal-compatible manual route□ Done __________	Coat the wafer with the selected positive MiR701 program; complete its bake and cool within this visit. Reference film 2 µm MiR701; 90°C / 90 s soft bake Program C-LITHO; no incompatible prime or strip chemistry Check Continuous film at mesa/gate steps; back and bevel clean. Record Recipe and film witness coat · morph-spin	NMOS · Across mesa · gate PMOS · Across mesa · gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
C045Expose NSELECTMLA150□ Done __________	Align and expose the released NSELECT pattern at its stack-specific dose. Keep the common origin and use at least two separated alignment marks. Wavelength 375 nm Dose and focus C-LITHO; measured on this film stack Check Both marks acquired; correct tone and device polarity. Record Dose, focus, alignment residual mla	NMOS · Along channel PMOS · Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
C046Develop NSELECTSVGDEV6 / accepted developer route□ Done __________	Complete PEB, development, rinse and dry as one track visit. Reference PEB 110°C / 90 s Reference development MF-26A / 60 s; calibrated endpoint Check Openings clear without attacking unprotected device silicon. Record Program; develop time develop	NMOS · Across mesa · source PMOS · Across mesa · source Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
C047Inspect NSELECTOptical microscope / linewidth tool□ Done __________	Confirm NMOS islands are selected while every PMOS island, including p+ S/D and gate edges, remains covered by mask B. Include the complete NMOS TiN gate landing/tab; exclude all PMOS gate tabs. Locations At least center and four radial sites Record CD and overlay against released enclosure limits Check No residual resist at intended openings; wrong polarity stops the wafer. Record Images and CDs index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C048Open NMOS diffusion windowsC-MASK metal-compatible oxide etch bench□ Done __________	Clear residual mask A plus mask B and gate oxide over selected NMOS S/D. Clear the corresponding mask films over NMOS TiN gate tops. Rinse and dry. NSELECT includes the NMOS TiN landing/tab so its subsequent contact depth matches the n-region stack. S/D clear depth Measured A residual + B + gate oxide Stop surfaces TiN at gate; Si at S/D; BOX in surrounding selected field Check No first-polarity opening is exposed; BOX and gate-edge loss within budget. Record Clear time and etch witness index · morph-etch	NMOS · Across mesa · source PMOS · Across mesa · source Isotropic wet polarity-window etch Wet etching opens NMOS S/D tops and sidewalls, retreats under mask/gate edges and recesses accessible BOX. PMOS remains sealed by its blocking oxide, including its sidewalls. TiN only shields channel oxide where its coverage remains continuous.
C049Remove NSELECT resistC-ROUTE TiN-compatible strip□ Done __________	Strip resist and clean residues while preserving the PMOS blocker and gate dielectric. Recipe C-ROUTE; no unsupported peroxide/oxygen plasma Check No resist enters source coating or RTA. Record Strip result index	NMOS · Across mesa · source PMOS · Across mesa · source Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
C050Clean exposed n-source/drain surfacesC-ROUTE bounded pre-SOD clean□ Done __________	Remove native oxide in open n-regions using the qualified short clean, then proceed directly to coating. Complete the designated DI rinse and dry before SOD coating; carry no liquid acid into the spinner. Budget Count oxide loss on all exposed TiN edges and BOX Check NMOS S/D clear; PMOS barrier remains adequate. Record Clean and queue index	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C051Coat phosphorus sourceDedicated accepted SOD spinner / Headway route□ Done __________	Coat the exact phosphorus source on the wafer and P-only plus B-then-P witness set. Use designated labware and source containment. Product / spin C-P; lot, age, dispense, rpm and duration Check No cross-use of source bottles/labware; back and bevel suitable for RTA. Record Source and coat log headway · morph-spin	NMOS · Across mesa · source PMOS · Across mesa · source Spin coating / wet phosphorus source The wet spin-on source reaches accessible tops and sidewalls and can gather at low corners. Its partly leveled profile is illustrative; actual wetting and corner thickness depend on the selected formulation. The exposed NMOS S/D faces receive source; the other polarity and channel edges depend on continuous blocking/gate coverage.
C052Cure phosphorus sourceDedicated SOD hotplate□ Done __________	Complete the selected cure and accepted transfer route. Temperature / time C-P Check Uniform, cured source film. Record Cure record index	NMOS · Along channel PMOS · Along channel Source cure / dry precursor The cure removes solvent and converts the wet source into the specified dry precursor. Some shrinkage and profile change are expected; the retained coating is not a second deposited layer.
C053Diffuse / activate n+ source and drainC-ROUTE accepted TiN + SOD thermal tool□ Done __________	Run the phosphorus cycle, including its effect on previously formed p+ regions and the common TiN gates. Record actual thermal history. Peak / dwell / ambient C-P Cumulative budget B + P diffusion and all mask/deposition heat included Check Both thermal-tool limits and p+ cumulative diffusion limits pass. Record Thermal trace and load map rtp · morph-fab	NMOS · Across mesa · source PMOS · Across mesa · source Phosphorus diffusion from exposed faces Dopant enters exposed silicon in contact with the source and spreads laterally as well as inward. The remaining source is converted glass; colored silicon is a qualitative doped volume, not a concentration contour. NMOS sidewalls can receive phosphorus; existing PMOS stays under mask B and experiences the same second thermal cycle.
C054Remove phosphorus source glassC-ROUTE source-glass wet bench□ Done __________	Strip source glass selectively; retain residual mask A/B as dielectric. Complete rinse/dry and avoid unnecessary HF overrun. Recipe C-P; measured glass/mask/TiN selectivity Check No P glass; no blocker cracks or BOX undercut beyond allowance. Record Strip endpoint and loss wetmetal · morph-fab	NMOS · Across mesa · source PMOS · Across mesa · source Source-glass removal The source glass is removed while the doped silicon remains. Accessible gate-edge oxide, masking oxide and exposed BOX may also recede according to the source-specific strip; the final loss requires measurement.
C055Measure the completed doping moduleMetrology / electrical witness station□ Done __________	Measure both n+ and p+ witnesses after their actual cumulative histories, including masked controls. Check remaining SOI silicon, TiN resistance and oxide-capacitor response. Measure C–V only on witnesses with a verified body electrode; transistor Vt is still extracted from actual FET transfer data later. Minimum dataset Rsheet n/p; masked controls; Si/BOX/mask loss; gate leakage/flat-band change Depth Use the released profile monitor to demonstrate adequate doping through remaining S/D film Check Neither polarity is silently counterdoped; no unacceptable gate-stack shift. Record Witness map and raw data hu · aist	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Order · dielectric and contacts

CUSTOMER-ORDER PROCESS

Retained A/B produces unequal contact depths. The common CONTACT mask is a deliberate process requirement: the shallow n+ and TiN contacts must survive while deeper p+ contacts clear.

Visit / destination	Operation, settings and check	Wafer after this visit
C056Clean before ILD depositionC-ROUTE accepted pre-PECVD clean□ Done __________	Remove source residues and organics without blanket-removing the retained oxide masks. Preserve Gate oxide, TiN, mask A/B and BOX Check Clean, dry accepted material history for deposition. Record Clean record index	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C057Deposit final interlayer dielectricOxford PECVD4 or accepted ILD chamber□ Done __________	Deposit oxide over the wafer, covering exposed NMOS S/D and gate topography continuously. Earlier mask oxides remain underneath. Target 300 nm additional SiO₂ Reference temperature 350°C; qualified ILD recipe Check Continuous coverage at gate corners; no cracking. Record Deposition witness pecvd · morph-deposit	NMOS · Across mesa · gate PMOS · Across mesa · gate PECVD / finite step coverage PECVD covers tops, steps and sidewalls with finite, recipe-dependent step coverage. Rounded contours show intended insulation; pinholes, seams and thin corners require witness checks.
C058Map contact depthsEllips2 / NanoDUV / step monitor□ Done __________	Measure the dielectric above n-S/D, p-S/D and gate landings using corresponding witness stacks. Record minimum and maximum contact clear depths. Nominal scale n-S/D ~300 nm; p-S/D ~500 nm, before actual mask/strip losses Gate landings Selection includes the same-polarity TiN tabs: intended n-gate ~300 nm; p-gate ~500 nm. Verify local residual films; tabs outside a selection can instead carry A+B+ILD. Check C-CONTACT window covers actual depth spread. Record Contact-depth map index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C059Coat CONTACT resistSVGCOAT6 or accepted metal-compatible manual route□ Done __________	Coat the wafer with the selected positive MiR701 program; complete its bake and cool within this visit. Reference film 2 µm MiR701; 90°C / 90 s soft bake Program C-LITHO; no incompatible prime or strip chemistry Check Continuous film at mesa/gate steps; back and bevel clean. Record Recipe and film witness coat · morph-spin	NMOS · Across mesa · gate PMOS · Across mesa · gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
C060Expose CONTACTMLA150□ Done __________	Align and expose the released CONTACT pattern at its stack-specific dose. Keep the common origin and use at least two separated alignment marks. Wavelength 375 nm Dose and focus C-LITHO; measured on this film stack Check Both marks acquired; correct tone and device polarity. Record Dose, focus, alignment residual mla	NMOS · Along channel PMOS · Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
C061Develop CONTACTSVGDEV6 / accepted developer route□ Done __________	Complete PEB, development, rinse and dry as one track visit. Reference PEB 110°C / 90 s Reference development MF-26A / 60 s; calibrated endpoint Check Openings clear without attacking unprotected device silicon. Record Program; develop time develop	NMOS · Across mesa · source PMOS · Across mesa · source Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
C062Inspect CONTACTOptical microscope / linewidth tool□ Done __________	Inspect contact enclosure inside n+/p+ S/D and TiN landing pads. Keep openings off mesa sidewalls and gate-channel edges. Include Kelvin/TLM chains for both polarities. Locations At least center and four radial sites Record CD and overlay against released enclosure limits Check No residual resist at intended openings; wrong polarity stops the wafer. Record Images and CDs index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C063Etch contacts through unequal dielectric stacksC-CONTACT metal-compatible oxide wet etch□ Done __________	Use the qualified selective oxide etch until the deepest approved contact clears. Track exposure time of the first-cleared n+ and TiN surfaces. Endpoint Measured deepest stack plus calibrated clear margin Selectivity C-CONTACT verified against Si, TiN and resist Alternate If the window fails, stop; separate contact masks are a documented redesign, not extra overetch Check All intended contacts clear; remaining Si/TiN pass minimums; no merged undercut holes. Record Etch timing and contact witness wetmetal · morph-etch	NMOS · Across mesa · source PMOS · Across mesa · source Isotropic wet contact etch The wet contact etch enlarges openings laterally beneath resist while clearing unequal oxide stacks. Rounded undercut walls are intentional in this view; different oxide layers can etch at different rates, so undercut is not inferred from one total depth.
C064Strip contact resistC-ROUTE metal-compatible strip□ Done __________	Remove resist and residues without oxidizing or thinning TiN beyond its allowance. Complete accepted rinse/dry. Silicon Exposed n+/p+ surfaces may regrow native oxide before metal; the final pre-metal clean handles it Check Contact bottoms free of organic residues. Record Strip log index	NMOS · Across mesa · source PMOS · Across mesa · source Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
C065Inspect contact openingsOptical microscope / witness inspection□ Done __________	Check contact bottoms, gate landings and separation. Use witnesses to verify clear rather than relying only on optical color. Critical locations Deepest p+ contacts and earliest-cleared TiN/n+ contacts Check No contact overlaps channel oxide or unintentionally joins nets. Record Contact images and dimension map index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Order · one metal interconnect

CUSTOMER-ORDER PROCESS

One Al–Si layer connects separate n/p TiN gates and source/drain regions over the ILD. This baseline measures as-deposited contacts first and does not silently include an aluminum alloying anneal.

Visit / destination	Operation, settings and check	Wafer after this visit
C066Final pre-metal surface cleanC-METAL wet clean / deposition load route□ Done __________	Clear contact native oxide and residue with the bounded, TiN-compatible pre-metal module. Transfer immediately to deposition. Method / dose C-METAL; include any sputter clean in total Si/TiN damage and loss budget Queue Record final-clean to vacuum time Check Contact surfaces clear; no uncontrolled ion mill into thin SOI or gate oxide. Record Clean dose, witness and queue index	NMOS · Along channel PMOS · Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
C067Deposit interconnect Al–SiMRC944 accepted Al–2%Si route□ Done __________	Deposit blanket Al–Si with the current permitted power and calibrated rate. Include a thickness and contact witness. Target 500 nm Al–2%Si Vacuum reference Base ≤5×10⁻⁷ Torr; 8 mTorr process reference Power Current C-METAL setting; do not copy historical 4 kW against a 3 kW target limit Check Continuous coverage of the actual contact aspect ratios. Record Power, pressure, rate and thickness sputter · morph-deposit	NMOS · Across mesa · source PMOS · Across mesa · source Sputter deposition / finite coverage Sputtered metal reaches horizontal surfaces and some sidewalls, with reduced coverage at steep or shadowed edges. Contacts are coated surfaces, not solid filled plugs; continuity requires measurement.
C068Measure metal filmStep-height / four-point witness station□ Done __________	Measure deposited thickness, film continuity and sheet resistance on a designated witness. Do not probe product metal where indentations could damage contacts or ILD. Film 500 nm target; current lot mean/range Check No peeling, pinholes or excessive contact-step voids. Record Thickness and sheet resistance index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C069Coat and cure metal BARCSVGCOAT3 / accepted post-metal coating track□ Done __________	Apply the released BARC film on Al–Si before aqueous-base resist development. Complete bake/cool within the same visit. Material AR3-600 reference; actual thickness from C-METAL Bake 190°C track reference; time and final cure from bound recipe Check Continuous protective film; Al–Si coverage survives the selected developer. Record Tool recipe, actual settings and completion time barc · sputter · morph-spin	NMOS · Along channel PMOS · Along channel Spin coating / cured BARC Spin-coated BARC partly levels the metal topography and is then cured. It can be thinner at convex edges and thicker in recesses; the drawing does not imply a uniform conformal film.
C070Coat METAL resistSVGCOAT6 or accepted metal-compatible manual route□ Done __________	Coat the accepted MiR701 resist on the cured BARC using the released reflective-metal lithography module. Preserve the BARC until its dedicated patterned opening visit. Reference film 2 µm MiR701; 90°C / 90 s soft bake Program C-LITHO; no incompatible prime or strip chemistry Check Continuous film at mesa/gate steps; back and bevel clean. Record Recipe and film witness coat · morph-spin	NMOS · Across mesa · gate PMOS · Across mesa · gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
C071Expose METALMLA150□ Done __________	Align and expose the released METAL pattern at its stack-specific dose. Keep the common origin and use at least two separated alignment marks. Wavelength 375 nm Dose and focus C-LITHO; measured on this film stack Check Both marks acquired; correct tone and device polarity. Record Dose, focus, alignment residual mla	NMOS · Along channel PMOS · Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
C072Develop METALSVGDEV6 / accepted developer route□ Done __________	Complete PEB, development, rinse and dry as one track visit. Reference PEB 110°C / 90 s Reference development MF-26A / 60 s; calibrated endpoint Check Openings clear without attacking unprotected device silicon. Record Program; develop time develop	NMOS · Across mesa · source PMOS · Across mesa · source Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
C073Inspect METALOptical microscope / linewidth tool□ Done __________	Inspect interconnect widths, pad openings, gate input straps and source/drain nets. The positive-resist pattern protects metal to keep. Locations At least center and four radial sites Record CD and overlay against released enclosure limits Check No residual resist at intended openings; wrong polarity stops the wafer. Record Images and CDs index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C074Open BARC beneath developed metal resistC-METAL metal-compatible masked plasma route□ Done __________	Clear BARC only in developed resist openings while retaining the metal-mask CDs. This is a patterned BARC open, not a blanket full-resist ash. Dose / recipe C-METAL calibrated thickness, time, chemistry and power Profile Verify resist remaining thickness and CD after open Check Al exposed only where it will be etched; protected wiring remains covered. Record Tool recipe, actual settings and completion time barc · lam7	NMOS · Along channel PMOS · Along channel Patterned plasma BARC opening Plasma clears BARC through the developed resist openings. Actual lateral BARC loss and resist erosion depend on the bound plasma program; the illustration does not assign a calibrated etch slope.
C075Etch aluminum interconnectLAM7 accepted Al–Si etch□ Done __________	Clear Al–Si outside protected wiring with the calibrated main/overetch program. End on ILD with minimum overetch. 7003 main reference 8 mTorr; TCP 800 W; bias 100 W; Cl₂/BCl₃ 90/45 sccm 7003 OE reference 8 mTorr; TCP 700 W; bias 100 W; Cl₂/BCl₃ 45/60 sccm Timing C-METAL calibrated for this 500 nm film; historical time mode is not assumed endpoint mode Check No residual metal fences or shorts; underlying dielectric retained. Record Trace and endpoint lam7 · morph-etch	NMOS · Across mesa · source PMOS · Across mesa · source Directional plasma metal etch Directional plasma etching removes exposed horizontal film and produces approximately vertical patterned edges. Lateral bias, selectivity and any sidewall residue remain recipe dependent.
C076Remove etch residue and resist immediatelyC-METAL corrosion-control / strip route□ Done __________	Complete the arranged post-Al-etch dechlorination and resist removal without a storage pause. Follow the released sequence for this metal history. Tool state Do not assume LAM7 in-tool strip is operational Finish Rinse/dry according to the current corrosion-control SOP Check No chloride corrosion or organic residue. Record Elapsed etch-to-clean time lam7	NMOS · Across mesa · source PMOS · Across mesa · source Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
C077Inspect finished wiringOptical microscope□ Done __________	Inspect pads, narrow metal gaps, contact edges and conductor crossings. Preserve images of representative defects as well as good sites. Map Center/edge and all test-die types Check No visible open or bridged metal. Record Inspection map index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Order · electrical release, dice and inspect

CUSTOMER-ORDER PROCESS

Probe before dicing, then repeat the relevant test on selected die. Bare die are unpassivated; environmental durability is not established.

Visit / destination	Operation, settings and check	Wafer after this visit
C078Check contacts and interconnect controlsEB-8 / parameter analyzer□ Done __________	Verify instrument wiring, then measure metal combs, gate line continuity and n+/p+ TLM/contact chains. Use four-terminal methods where provided. Initial stress Low voltage/current; increase only after stable linear contacts Handle Record C-TEST handle/back-gate condition Check Both contact polarities are acceptably ohmic and repeatable; no gate-to-metal or inter-island shorts. Record Raw contact/comb data probe · contacts	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C079Screen NMOS and PMOS devicesEB-8 / parameter analyzer□ Done __________	Measure gate leakage, forward/reverse transfer and low-drain-voltage output curves for both polarities. Use matched rest history and handle condition. NMOS start VS=0; VDS=+0.05 V; VGS 0→+1→0 V PMOS start VS=0; VDS=−0.05 V; VGS 0→−1→0 V Initial compliance ID 10 µA; IG 10 nA, then raise only after stable contact/leakage checks Extension Only to released C-TEST operating range Check Enhancement-mode margin, leakage, hysteresis and on-current pass the actual specification. Record Raw sweeps, dwell, compliance, geometry and handle state probe · hu	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C080Measure complementary logicEB-8 / oscilloscope test setup□ Done __________	Measure inverter DC transfer and supply current, then NAND/NOR and transmission-gate checks. Test ring oscillators with their output buffers and known probe loading. Supply Begin at a released low VDD and extend to C-TEST value Evidence Noise margins, rail approach, short-circuit/static current and dynamic operation Check Both polarities cooperate with adequate logic margins; isolated FET operation alone is insufficient. Record Circuit truth tables, transfer and frequency data probe	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C081Run customer die test and wafer mapElectrical wafer-test station□ Done __________	Execute the released test vector set on each die intended for shipment. Save failures as well as passes and log a denominator for yield. Release C-TEST product specification; no compliance-limited pass Retain At least one undiced reference and process-monitor results Check Every shipped die is traceable to a passing test record. Record Wafer map, test revision, die pass/fail and timestamp index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C082Apply dicing protectionAccepted post-metal coat station□ Done __________	Apply the qualified removable protective coating over the unpassivated front surface. Keep pads and coatings compatible with the post-dice removal method. Recipe C-TEST dicing protection; no high-temperature bake outside metal budget Check Film covers active area without inducing corrosion. Record Protective coat recipe index · morph-spin	NMOS · Across mesa · gate PMOS · Across mesa · gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
C083Mount wafer for dicingDicing preparation station□ Done __________	Mount the protected wafer on the selected tape/frame and align the scribe lanes. Record orientation and original die map. Tape / frame C-TEST compatible with wafer thickness and later die removal Check No trapped particles or bow that compromise cuts. Record Mount and alignment record index	NMOS · Along channel PMOS · Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
C084Dice waferDisco DAD3240 / released dicing route□ Done __________	Cut the predefined streets using the selected blade, feed, spindle and water settings for this SOI/metal stack. Recipe C-TEST; cut-depth and front/back chipping limits Check No cuts into pads or active regions; no catastrophic edge damage. Record Blade, recipe, kerf and cut log index	NMOS · Along channel PMOS · Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
C085Remove dicing protection and dryAccepted post-metal die-cleaning bench□ Done __________	Remove protective coating and dicing residue by the released metal-compatible route. Rinse/dry without leaving water trapped at die edges. Chemistry / temperature C-TEST; do not use an unqualified aggressive oxide or metal strip Check No residue or aluminum corrosion. Record Cleaning completion index	NMOS · Across mesa · source PMOS · Across mesa · source Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
C086Inspect and retest representative diced dieDie microscope / electrical fixture□ Done __________	Inspect edges and pads; repeat the required electrical checks on representative die and all units required by the shipment specification. Mechanical Chipping and contamination limits Electrical Same supply, handle condition and pass criteria as wafer test Check Dicing/cleaning did not change the accepted behavior. Record Die images, retest data and elapsed order time index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
C087Place tested die in identified carriersClean die-pack station□ Done __________	Load passing die into clean labeled carriers with orientation, pinout, measured operating limits and wafer/die traceability. Product description Unpassivated research bare die; qualification level stated Clock stop Tested, cleaned, inspected die ready for dispatch Check Correct die IDs and test records accompany each carrier. Record Packing and completion timestamps index	NMOS · Along channel PMOS · Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Completion criteria

Before product lots: demonstrate isolation, both diffusion-mask blockers, TiN/oxide electrical stability through the entire B-then-P history, retained SOI thickness and a contact-etch window for the actual unequal depths.
Each lot: record n+/p+ sheet resistance on isolated monitors, both TLM/contact-chain results, oxide/TiN thickness controls and leakage/transfer/output measurements with a defined handle condition.
Circuit release: test inverter transfer/gain/noise margins, NAND/NOR and transmission-gate operation, dynamic ring oscillators and all customer-accessible circuits at the specified supply. A ring oscillator alone does not establish yield.
Production status requires repeated lot data, a measured die-yield denominator, calibrated design rules/models and recorded order-to-tested-die elapsed time. Those data do not yet exist for this proposed traveler.
Optional passivation adds dielectric deposition and a PAD-opening lithography level before final test/dicing; it is not included in the six-level count. Protective packaging and environmental reliability remain separate development work.

Process references and source notes

index Berkeley NanoLab equipment manual index
Read 21 Sep 2026. Lists material-control, lithography, thermal, TiN-candidate PVD/metal-etch, metrology and dicing tools. Listing does not certify this process route.
materials NanoLab materials control and compatibility
Existing traveler reference; full document did not render in the current web reader. Current staff/tool restrictions govern each wafer-history transition.
aist Liu et al., SOD diffusion and minimal SOI CMOS, JJAP 56 06GG01 (2017)
Abstract confirms phosphorus/boron SOD, TiN-gated SOI CMOS and working circuits; identifies boron-glass removal and silicon consumption. The accessed abstract does not establish this gate-first sequence or wafer specification.
aistabs Accessible author-paper abstract and bibliographic record
Abstract read 21 Sep 2026; full text not available here. Literature temperatures from citing articles are not incorporated as NanoLab recipes.
hu Chenming Hu, MOS capacitor physics
Workfunction, oxide charge and threshold electrostatics; no measured TiN workfunction or threshold is assigned to this process.
soiphysics Chenming Hu, thin-body SOI and transistor scaling
Thin-body electrostatics and SOI tradeoffs; not a fabrication recipe.
wet6 MSINK6 MOS cleaning
Campaign use before TiN/SOD only; source retained from earlier reviewed traveler.
wetmetal MSINK5 refractory metal processing
Current index links this bench. Exact TiN/SOD and HF handling route remains C-ROUTE.
oxide Tystar1 MOS gate oxidation
Earlier review: 1GATEOXA, 1050°C maximum. The 15 nm target requires current growth calibration and runs before TiN/SOD.
tinpvd Oxford thin-film deposition cluster / PVD1
Current inventory candidate. No TiN gas/power/deposition-rate recipe was verified; use C-TIN.
tinet Centura-MET metal etch chamber
Current inventory candidate for TiN patterning; exact TiN/SiO₂ selectivity and clean route remain unverified.
coat SVGCOAT6
Earlier reviewed MiR701 2 µm recipe: 90°C/90 s soft bake; current recipe/version must match loaded program.
develop SVGDEV6
Earlier reviewed MiR701: 110°C/90 s PEB and MF-26A/60 s; actual stack dose/CD remain calibrated.
mla MLA150 maskless lithography
375 nm and 150 mm operation from earlier review; published alignment accuracy does not include etch bias or all edge-placement errors.
lam8 LAM8 silicon / poly etch
Campaign silicon etch candidate before metal. The old 150 nm poly timing is not adopted for 60 nm single-crystal SOI.
headway Headway manual spinner
Spinner inventory and handling reference; B/P SOD needs dedicated, accepted bottle/labware procedures.
rtp RTP3 Si non-MOS RTA
Earlier reviewed time/temperature envelope: 1100°C maximum, with duration limits dependent on temperature. No accepted TiN-plus-SOD process is asserted.
pecvd Oxford PECVD4
Earlier reviewed 1010 oxide at 350°C: Ar/N₂O/N₂/10%-SiH₄-in-Ar 650/150/200/50 sccm; 81 MHz 200 W; 1000 mTorr; reported rate 171 nm/min. Mask blocking, density and film-specific rates remain unqualified.
sputter MRC944 Al–2%Si sputtering
Earlier review: 5×10⁻⁷ Torr base target, 8 mTorr reference; T3 power limit 3 kW conflicts with historical 4 kW data. Do not use 4 kW without a current permitted recipe.
lam7 LAM7 aluminum etch
Earlier 7003 family main/OE reference. Endpoint and immediate corrosion-control route require release; in-tool strip was documented offline.
probe Everbeing EB-8 electrical measurements
HP4145B, 4284A and four manipulators listed in earlier reviewed manual. Verify installed instruments and wiring.
contacts MIT 6.720J metal–semiconductor contacts
Contact barriers and doping; metal placement is not proof of an ohmic contact.
semi SEMI oxide/nitride RIE
Process acceptance is case reviewed; a possible metal-history dielectric etcher if a plasma contact route is developed. Contact-depth spread and thin-Si/TiN selectivity must be proven.
wet8 MSINK8 processed-wafer preclean
Pre-metal campaign cleaning before MSINK6. Not used after TiN deposition or after a disqualifying general-sink history.
barc SVGCOAT3 BARC and lift-off coating
AR3-600 BARC and 190°C track reference. Actual metal-protection thickness/cure and patterned plasma opening require calibration.
morph-spin MicroChemicals: spin coating over textured substrates
PDF pp. 1 and 4 explain edge pullback and accumulation in holes/spaces. Direct evidence for resist morphology; analogous leveling shown for SOD is a qualitative liquid-flow inference, not measured coverage for a chosen dopant formulation.
morph-fab Chenming Hu: Device Fabrication Technology, chapter 3
PDF pp. 3–5 and 10–12 support silicon-consuming thermal oxidation, lateral wet-etch retreat and directional plasma etching. The diagrams do not assign calibrated etch angles, undercuts or diffusion lengths.
morph-deposit MEMS Exchange: deposition processes and step coverage
Explains CVD/PVD step-coverage differences and silicon consumption during oxidation. LPCVD wrap, finite PECVD coverage, directional evaporation and reduced PVD sidewall coverage are qualitative morphology conventions.
morph-etch MEMS Exchange: isotropic and anisotropic etching
Distinguishes isotropic lateral undercut, crystallographic wet etching and directional RIE. The mesa route here is directional plasma etching, not a KOH crystal-plane etch.