PROCESS DEVELOPMENT · CLEANROOM TRAVELER
Target NMOS · SOI production flow
Four patterned levels · self-aligned polysilicon gate · phosphorus spin-on doping · one interconnect metal
This is the target process for turning the bulk NMOS experiments into repeatable, circuit-capable SOI research dies. Mesa isolation separates device islands, the polysilicon gate defines the source/drain edges, and an interlayer dielectric plus contacts lets metal cross gates and join transistors. It is a development target with explicit release measurements, not an already qualified production recipe.
The starting choice is a moderately p-doped, approximately 200 nm silicon film with 30 nm thermal gate oxide and 150 nm polysilicon. That choice preserves the familiar n+ poly NMOS approach; it is intentionally different from the much thinner, lightly doped TiN CMOS architecture. A single phosphorus SOD module dopes the exposed source/drain silicon and the poly gate. Its required junction depth and gate activation are measured rather than inferred from a nominal anneal.
For the under-24-hour service, prepare and qualify fixed mesa layouts and blanket oxide/poly stacks in campaigns, then start each order at GATE lithography. Orders use GATE, CONTACT and METAL; custom mesa geometry adds MESA and the front-end preparation back to the order. The baseline ships unpassivated bare research dies with floating transistor bodies, so body-history effects, packaging conditions and electrical limits are part of the product definition. Timing and yield must be demonstrated before being advertised.
- Incoming wafer — proposed baseline
- 150 mm SOI, (100) device silicon, tool-compatible SEMI flat and handle thickness; device film 200 ±10 nm, boron nominal 3×10¹⁶ cm⁻³ (initial procurement window ±20%); BOX ≥400 nm. Confirm supplier capability and the actual lot.
- Gate stack
- 30 nm dry thermal SiO₂ target, initially ±5% film acceptance; 150 nm undoped LPCVD poly target, initially ±10 nm. Growing 30 nm SiO₂ consumes about 13 nm Si before later consumption or etch losses.
- Patterned levels
- M1 MESA → M2 GATE → M3 CONTACT → M4 METAL. Positive resist exposes material to REMOVE at MESA/GATE/METAL and exposes openings at CONTACT.
- Initial design envelope
- Proposed L ≥5 µm; qualification ladder 5/10/20/50 µm. Start with ≥10 µm contacts and metal width/space, and measured enclosure margins. Nominal supply target 3.3 V; 5 V is a separate characterization extension, not an initial rating.
- Body and isolation
- Device silicon islands are isolated by etched gaps and the BOX. The body is floating; a source terminal is not a body contact. Handle/chuck coupling is recorded separately. No p+ body tie or depletion-load implant is included.
- Stocking boundary
- After accepted MESA isolation, gate oxidation and blanket poly deposition. Fixed-island wafers are stored in qualified dry, sealed carriers; lot age and retained monitor results follow each order.
- Finish
- 400 nm PECVD SiO₂ ILD and 500 nm Al–2%Si interconnect, both proposed targets. Probe, dice, clean and package as bare research die. Passivation with pad openings would be a fifth mask.
Step explorer
Listed sequence ↓Sections are cut from the same 3D material geometry. Film thickness, etch bias and diffusion lengths are exaggerated; coverage must be verified on the actual wafer.
Geometry and coverage
Views are schematic, not to scale. The main cut passes along source–channel–drain; the gate landing extends onto BOX outside that cut. Film thicknesses and lateral dimensions are specified in the traveler, not measured from the illustration. The n+ volumes indicate exposed regions that receive phosphorus. They do not claim uniform concentration, a measured diffusion depth or junctions reaching the BOX. Residual p-type silicon under source/drain is permitted by this baseline. The intended poly gate crosses the mesa width, wraps its channel-side edges and extends onto BOX. LPCVD coverage makes this feasible, but gate continuity, unwanted sidewall stringers, oxide undercut and mesa-edge leakage require physical/electrical checks. The body has no terminal. BOX separates it from the handle, so grounding a chuck does not ground the transistor body. No four-terminal threshold or body-bias claim follows from these drawings. ILD remains underneath metal wherever contact holes are absent, including metal crossing a gate. A gate-to-metal contact lands on a widened poly pad on BOX; source/drain contacts land only inside their doped active regions. Morphology is illustrative rather than a dimensional prediction: directional plasma etches have steep walls, wet oxide etches retreat laterally, thermal oxidation consumes silicon, and deposited films follow their stated deposition method. Numerical geometry is deliberately exaggerated for legibility. Spin-on resist, BARC and dopant source films wet accessible relief and partially level it. Convex corners may be thin and recesses thick; a smooth drawing is the intended coverage, not evidence of pinhole-free coating. Wet, baked and thermally converted source states are distinguished. BOX isolates separate silicon islands; it does not prevent doping of an exposed mesa sidewall. After source/drain oxide clearing, SOD can contact those sidewalls and supply dopant inward. Only the channel segment retains the intended oxide/gate wrap, subject to continuity, lateral etch retreat and diffusion limits. Use the transverse channel section to inspect the gate/oxide wrap and the transverse source/drain section to see exposed mesa faces. The longitudinal section alone hides the channel-side edges. At the channel, the gate mask encloses the complete film wrap on both mesa sidewalls and extends onto BOX on both sides. The contact tab is intentionally one-sided; protective enclosure is required at both edges. No enclosure dimension can be read from this exaggerated drawing.
N001 · Receive and inspect the SOI lot
Read wafer IDs and orientation, inspect both faces, and assign device, film, mesa-etch and electrical-monitor wafers. Keep device wafers off contact metrology surfaces.
Lot recipe assignments
Use these assignments wherever their IDs appear in the sequence. Complete the values before starting the affected module.
| Assignment | Value for this lot | Context |
|---|---|---|
| N-ROUTE Complete wafer-history route | Enter accepted tool IDs for source-present SOD heating, glass stripping, post-SOD clean, ILD, contact etch, metal, sinter and dicing. | Use the actual SOD bottle, carriers, backside films and every earlier tool in this route. The listed Berkeley tools are nominal candidates. Processing in MSINK16/18 prohibits later MSINK1/6/7/8 use; if that route is selected, bind all downstream cleans and deposition/etch tools accordingly. A rinse does not restore MOS eligibility. No post-SOD return to Tystar1/Tystar10 is in this flow. |
| N-OX Gate oxidation | Tystar1 1GATEOXA or its current replacement: bind temperature, dry oxidation time, gas segments, N₂ anneal and cooldown to the current 30 nm monitor calibration. | The target thickness is fixed; an oxidation time is not extrapolated from the old traveler. Transfer to Tystar10 follows the current MOS-furnace transfer procedure. |
| N-LITHO Four lithography programs | Bind MESA/GATE/CONTACT/METAL MLA150 dose, focus, alignment mode, resist program, development and measured bias on each actual stack. | MiR701 2 µm and the documented coat/develop references below are starting references. The four exposures do not automatically share a dose. Metal lithography includes BARC to protect Al from TMAH-containing developer. |
| N-ETCH Mesa, poly and oxide clears | Bind LAM8 mesa/poly endpoint plus overetch, native/gate-oxide wet clear, post-SOD glass strip and CONTACT etch with measured silicon/oxide losses. | Include sidewall stringer removal, BOX loss and gate-edge undercut. A water-break observation alone does not establish glass removal or an undamaged dielectric. |
| N-P-SOD Phosphorus SOD module | Enter manufacturer/product/lot, dispense, spin, cure, source-present thermal tool/carrier, ambient, ramp, peak, dwell, cooldown and glass-removal chemistry. | Use a qualified version of the user’s phosphorus process. Historical P509 literature explored 900–950°C and tens of seconds; that is not a released recipe for this SOI/poly stack. Qualify active silicon and poly separately. Reaching the BOX is not a release requirement. |
| N-ILD Interlayer oxide | 400 nm PECVD SiO₂ target; bind chamber, accepted post-SOD history, temperature, measured rate and stress. | PECVD3 is the nominal cleaner route if accepted. Its standard lists 400°C while the manual gives a general ≤350°C recommendation; select the accepted program. PECVD4 is not an automatic substitute: if selected, qualify the complete subsequent path, with SEMI a possible case-reviewed contact-etch tool rather than assuming MxP eligibility. |
| N-CONTACT Contacts and aluminum | Bind minimum native-oxide removal, maximum Si/poly recess, metal preclean dose, MRC944 deposition calibration, LAM7 etch/corrosion sequence and post-metal anneal. | The measured n+ profile must remain underneath the maximum contact recess and any metal interaction. Historical 2 min sputter cleaning and 4 kW MRC power are not adopted. |
| N-BARC Metal-protection BARC module | Bind AR3 coating thickness/spin/cure and a metal-compatible masked O₂ BARC-open program with measured lateral bias and resist loss. | MRC944 recommends BARC because TMAH developer attacks Al. This is not a blanket resist strip: clear BARC in developed openings while retaining the metal mask. No generic full Matrix ash or metal-prohibited etcher is assigned. |
| N-FINISH Sinter, singulation and handling | Enter a metal/SOD-history-compatible anneal tool/program, protective coating, dicing saw/mount, die clean, dry and conductive-safe carrier. | A 350–400°C contact/passivation treatment is a development candidate only. Tystar18 requires its own history eligibility; RTP3 cannot be assigned an invented 20 min recipe. Bare-die shipment and packaging are the initial product boundary. |
| N-RELEASE Lot release and operating envelope | Freeze numeric Vt, leakage, contact resistance, Rs, dimensional, isolation, history, temperature and circuit limits from qualification lots; identify revision and sample plan. | Suggested engineering targets below are starting gates, not measured capability. Include actual order start, process end, tested-die ready and shipment times when evaluating the 24-hour objective. |
Cleanroom sequence
74 visitsEach numbered visit follows the wafer to a tool, bench or measurement station. The section at right shows the intended structure after that visit.
Campaign · receive and isolate SOI
BATCH PREPARATIONPrepare standard device islands before customer orders. Retain a full-wafer furnace witness set and a matched SOI process monitor; the real wafers remain in their accepted cleanliness route.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N001Receive and inspect the SOI lotClean inspection station / accepted wafer carrier□ Done __________ | Read wafer IDs and orientation, inspect both faces, and assign device, film, mesa-etch and electrical-monitor wafers. Keep device wafers off contact metrology surfaces.
Check No cracks, edge chips in handling zones, unexplained backside films or mismatched substrate lot. Supplier concentration is not a measured active-film profile. Record Lot certificate, map origin, wafer/monitor IDs | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N002Map the incoming SOI filmsEllipsometry · accepted SOI model□ Done __________ | Measure a calibrated c-Si / SiO₂ / Si stack at center and radial sites; use a 25-point map for campaign qualification. Archive model assumptions and residuals.
Check A low fitting error does not remove thickness/index correlation; reject a fit that disagrees with the physical step witness. Record tSi and tBOX maps, model, fit quality | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N003Clean before mesa lithographyMSINK8 · history-compatible organics route□ Done __________ | Run the accepted organic clean, rinse and dry for incoming SOI. Use only the bound native-oxide treatment; account for every HF exposure in the BOX budget.
Check Particles and organic residues absent; clean wafer loaded into the specified carrier. Record Bath/program, rinse/dry and clean-to-coat time | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N004Coat M1 MESA resistSVGCOAT6□ Done __________ | Dehydrate/prime and coat the mesa mask using the calibrated MiR701 program. The protected resist defines silicon islands to retain.
Check Continuous resist across the active area; edge bead cleared as required for the etcher. Record Program revision and measured film | Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell. |
| N005Expose M1 MESAMLA150□ Done __________ | Expose the complement of the device islands and protected alignment marks. Use the common wafer origin and the lot-specific focus/dose.
Check Pattern conversion, field boundaries and clear/keep tone agree with the signed mask view. Record File hash, dose/focus, origin | Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit. |
| N006Develop M1 MESASVGDEV6□ Done __________ | Run the bound post-exposure bake, development, rinse and dry as one track visit.
Check Exposed gaps clear to the substrate; islands remain intact. Record Program and actual timing | Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result. |
| N007Inspect mesa lithographyUV optical microscope / CD metrology□ Done __________ | Check the island boundaries, alignment marks, gaps and resist clearing before etch.
Check No resist scum connecting islands and no resist breaks inside intended silicon. Record CD, defect map, photographs | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N008Etch device silicon to the BOXLAM8 · accepted crystalline-Si recipe□ Done __________ | Run the calibrated SOI mesa etch on the monitor first, then device wafers. Stop on BOX with only the overetch needed to clear residual silicon and corner filaments.
Check Exposed BOX is electrically isolating and physically clear; protect the required BOX thickness. Record Endpoint trace, actual overetch and monitor result | Directional plasma mesa etch Directional Si etching clears the gaps to BOX and leaves approximately vertical mesa walls. BOX separates silicon islands; it does not block dopant entry through a later-exposed mesa face. |
| N009Strip mesa resistMatrix asher□ Done __________ | Remove the full resist thickness using the accepted strip, including any hardened residue. This is a strip, not a brief descum.
Check No visible resist film or edge residue remains. Record Recipe/time and wafer temperature record | Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss. |
| N010Clean the etched mesasMSINK8□ Done __________ | Remove post-etch organics with the oxide-preserving version of the accepted clean; rinse and dry. Avoid an automatic long HF step.
Check No etch residue or water marks; wafer remains eligible for the MOS gate preparation route. Record Clean and transfer history | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N011Measure mesa heightAlpha-step or accepted profilometer · monitor wafer□ Done __________ | Measure the device-layer step on the designated witness and compare it with the incoming ellipsometry map. Keep stylus marks off device wafers.
Check No unexpected silicon loss and no stepped residue masquerading as the BOX stop. Record Step traces and monitor ID | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N012Check exposed BOX and mesa edgesEllipsometry / optical inspection on monitor□ Done __________ | Measure the exposed BOX window and inspect residual-silicon test areas. Perform SEM only on a sacrificial companion if the optical/electrical witness is inconclusive.
Check The blank BOX area is clear and the mesa edges have no conducting skirt. Record BOX map and edge images | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
Campaign · make and stock the gate stack
BATCH PREPARATIONAll MOS furnace work occurs here, before the SOD route. The polysilicon stack can be stocked only for the fixed mesa geometry associated with its wafer map.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N013Clean immediately before gate oxidationMSINK6□ Done __________ | Run the current MOS pre-furnace clean accepted for patterned SOI, including the specified final native-oxide removal, rinse and dry. Transfer in the designated clean carrier.
Check No organic/metal contamination; final cleaning does not undercut the mesa beyond the dimensional allowance. Record Bath/program, start/end and transfer time | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N014Grow the gate oxideTystar1□ Done __________ | Grow the dry thermal gate dielectric on mesa tops and sidewalls using the bound recipe; run matching oxide witnesses in the same load. Complete the bound N₂ anneal and cooldown.
Check Full recipe and loading trace complete. No fixed growth time is inferred from an old nominal rate. Record Boat positions, temperature/time/gas trace | Thermal oxidation / silicon consumption Oxide grows by consuming exposed mesa-top and sidewall silicon while expanding outward. No new blanket thermal film is deposited on the exposed BOX. Nominal 30 nm oxide consumes about 13 nm Si; local corner shape is schematic. |
| N015Measure the oxide witnessEllipsometry · oxide monitor only□ Done __________ | Map the matching oxide witness while keeping device wafers in the accepted clean furnace-transfer path. The monitor returning from general metrology is not silently substituted back into the MOS lot.
Check Witness passes thickness/uniformity and the oxide’s electrical monitor program. Device queue remains inside N-OX. Record Thickness map and gate-oxide witness IDs | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N016Deposit the blanket poly gate filmTystar10□ Done __________ | Transfer eligible device wafers directly by the approved MOS-furnace route and deposit undoped LPCVD poly. Include a thickness witness; retain the gate oxide rather than stripping it during transfer.
Check Recorded transfer is accepted; no unplanned wet re-clean removes or damages the gate dielectric. Record Recipe, duration, thickness witness, load and transfer times | LPCVD poly / wrapping step coverage LPCVD poly follows the oxide across mesa tops, down sidewalls and onto BOX. The eventual gate pattern retains its channel-side wrap; unwanted conductor around source/drain edges must be cleared. |
| N017Measure the poly witnessNanoduv / accepted film metrology□ Done __________ | Measure the designated poly witness with the correct poly/oxide optical model. Correlate periodic physical thickness measurements during qualification.
Check Thickness and particles within the bound process window; oxide/poly films are not confused by a single-layer fit. Record tpoly map, model and monitor ID | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N018Inspect and seal the campaign stockClean inspection station / dry storage carrier□ Done __________ | Inspect the completed stack, seal device wafers in the qualified dry carrier, and assign each wafer its fixed MESA layout revision. Retain witness and storage-age records.
Check Campaign monitor qualification is linked to the stock lot; the incoming device islands match the order’s allowed placement grid. Record Carrier/location, seal date, film maps and layout revision | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
Order · self-aligned gate pattern
CUSTOMER-ORDER PROCESSStart the customer-order clock at stock withdrawal. Only GATE, CONTACT and METAL remain patterned for a fixed mesa template.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N019Withdraw and inspect the stocked waferClean inspection station□ Done __________ | Verify stock age, carrier seal, stack maps and alignment marks against the order. Inspect handling surfaces and transfer to the lithography carrier.
Check No broken seal, particles or film change outside the storage qualification. Record Order start timestamp, wafer ID and incoming photos | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N020Coat M2 GATE resistSVGCOAT6□ Done __________ | Run the bound prime/coat/soft-bake program over the poly topography; inspect wafer edge and coverage across mesa steps.
Check No thinning/pinholes at gate-critical mesa edges. Record Coat program and film thickness | Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell. |
| N021Expose M2 GATEMLA150□ Done __________ | Align to the MESA marks. Expose the poly to remove; retain gate strips and widened contact tabs on BOX. Extend each gate beyond both side edges of its silicon island.
Check Gate crosses the full mesa width. An open path around a gate end must not connect source and drain. Record Alignment residual, dose/focus and mask hash | Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit. |
| N022Develop M2 GATESVGDEV6□ Done __________ | Run the bound PEB/develop/rinse/dry program.
Check Gate lines and pads intact; exposed poly clear of scum. Record Program and timing | Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result. |
| N023Inspect gate dimensions and enclosureOptical microscope / CD metrology□ Done __________ | Measure the printed gate lengths and gate-end enclosure at both mesa sidewalls. Confirm the gate mask extends beyond both wrapped edges onto BOX; inspect pads and isolation around adjacent islands.
Check Dimensions and overlay fit the qualified process window; neither mesa edge has a gate neck or end gap. Record CD/overlay table and defect images | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N024Etch the polysilicon gateLAM8□ Done __________ | Etch exposed poly to oxide with the bound breakthrough/main/overetch program. Include a matching stepped witness to establish removal of mesa-sidewall poly stringers.
Check Unwanted poly outside the gate is cleared; the intended gate and its underlying oxide remain continuous down both channel-side mesa walls and onto BOX. Record Etch trace, endpoint and clear witness | Directional plasma gate etch The directional etch defines the gate but can leave conductor on steep mesa walls. This nominal drawing assumes the required overetch has cleared those stringers; confirm that result on the stepped witness. Inspection does not remove a residue. |
| N025Strip the gate resistMatrix asher□ Done __________ | Remove all gate resist and etch-organic residue with the accepted full strip.
Check Gate edges free of organic residue. Record Recipe and actual duration | Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss. |
| N026Clean after gate etchMSINK8□ Done __________ | Run the accepted post-resist clean while preserving the thin thermal gate oxide until the deliberate source/drain clear.
Check Clean poly/oxide surface; source/drain oxide not accidentally over-stripped. Record Clean and cumulative oxide loss | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N027Verify poly isolation on the stepped companionOptical inspection / SEM on sacrificial witness□ Done __________ | Inspect both mesa sidewalls, their feet and the gate ends on the matched dummy, using opposed tilted views when needed. Distinguish the retained channel gate wrap from unwanted S/D-sidewall poly; retain device wafers in their accepted clean carrier.
Check Gate wrap is intact on both sides; no unwanted sidewall conductor bridges. The SEM-exposed dummy does not return to the device route without an approved path. Record Images and witness disposition lam8 · materials · morph-etch | Sidewall-clear inspection Inspect the stepped witness for residual poly outside the intended gate. The subsequent nominal geometry assumes this required check passes; it retains the gate wrap only at the channel, not around all source/drain mesa edges. |
| N028Clear exposed gate oxide self-aligned to polyMSINK7 or bound accepted oxide bench□ Done __________ | Etch the thermal oxide from exposed source/drain silicon, complete the accepted QDR/SRD rinse/dry sequence, and transfer dry wafers in the designated carrier. The gate retains oxide underneath; the BOX is also exposed to this etchant and its loss must be included. Exposed source/drain mesa sidewalls may clear along with their tops; do not treat the BOX as a sidewall diffusion barrier.
Check S/D silicon is exposed; retained gate/oxide coverage is continuous at both channel-side mesa edges, within the undercut and BOX-loss budgets. Record Bath, temperature, actual time, rinse/dry and oxide-loss witness | Isotropic wet oxide clear Wet etching exposes S/D tops and sidewalls and also recesses accessible BOX. Channel-side oxide survives only under the retained gate wrap and within the lateral-undercut budget; BOX does not shield exposed mesa sidewalls from the source. |
Order · phosphorus SOD and first process evidence
CUSTOMER-ORDER PROCESSThe same module must produce conductive source/drain silicon and gate poly. No post-SOD MOS furnace return is included.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N029Coat the phosphorus sourceHeadway1 / accepted SOD coating station□ Done __________ | Transfer the oxide-cleared wafer promptly to the approved station and coat the exact bound phosphorus formulation. Process separate single-crystal SOI and poly witnesses in the same module.
Check Continuous source coverage on the intended top and exposed S/D side faces; inspect corner minima and wetting. No unaccepted backside deposit, particles or incompatible carrier contamination. Record Bottle/spin records and witness IDs headway · sod · morph-spin | Spin coating / wet phosphorus source The wet spin-on source reaches accessible tops and sidewalls and can gather at low corners. Its partly leveled profile is illustrative; actual wetting and corner thickness depend on the selected formulation. Exposed S/D mesa faces receive source; the channel depends on continuous retained oxide/poly coverage. |
| N030Cure the source filmAccepted exhausted hotplate / oven□ Done __________ | Run the product-specific solvent-removal and source conversion program. Cool and transport with the specified clean handling.
Check Source is in the required dry state for the bound thermal tool, with no cracking or gross nonuniformity. Record Cure trace, film appearance and time | Source cure / dry precursor The cure removes solvent and converts the wet source into the specified dry precursor. Some shrinkage and profile change are expected; the retained coating is not a second deposited layer. |
| N031Diffuse phosphorus and activate the polyBound source-present thermal tool · RTP3 candidate□ Done __________ | Run the complete bound purge, ramp, hold and cooldown. Record the calibrated temperature trace for this backside/emissivity stack and source-bearing wafer.
Check Actual thermal exposure inside the qualified window; source/thermal history remains attached to the wafer. Record Trace, sensor/calibration, chamber and actual peak/dwell | Thermal diffusion from exposed faces Dopant enters exposed silicon in contact with the source and spreads laterally as well as inward. The remaining source is converted glass; colored silicon is a qualitative doped volume, not a concentration contour. Dopant can enter S/D mesa sidewalls as well as their tops. This baseline allows p-type Si to remain below the top junction; no full-film conversion is implied. |
| N032Remove the phosphorus source glassBound glass-strip wet station□ Done __________ | Strip the converted source with the product-specific, history-compatible process, then rinse and dry. Avoid etching from an assumed source-glass rate equal to thermal oxide.
Check No remaining source glass or residue; gate oxide survives at edges and poly is not damaged. Record Strip time, rinse/dry and witness loss | Source-glass removal The source glass is removed while the doped silicon remains. Accessible gate-edge oxide, masking oxide and exposed BOX may also recede according to the source-specific strip; the final loss requires measurement. |
| N033Measure remaining films on the monitorEllipsometry / accepted film metrology□ Done __________ | Measure oxide-loss and SOI-consumption witnesses and compare against their pre-SOD maps. Use a model appropriate to doped silicon; verify ambiguous fits physically.
Check Film consumption fits the contact and isolation budgets; thickness alone is not electrical oxide qualification. Record Before/after film maps | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N034Measure doped SOI sheet resistanceCDE ResMap / accepted four-point station · SOI witness□ Done __________ | Map the exposed SOD-doped SOI monitor using correction factors and probe force suitable for its film. Keep probes off product transistor areas.
Check Map within N-RELEASE distribution; no open/discontinuous active film. Record Rs map, probe spacing/force and correction | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N035Measure doped poly sheet resistanceAccepted four-point station · poly witness□ Done __________ | Measure the poly witness independently of SOI. Maintain a campaign MOS-capacitor check for poly depletion and oxide charge after the same SOD sequence.
Check Poly resistance and electrostatic monitor agree with the gate model and delay budget. Record Poly Rs map and capacitor-monitor linkage | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N036Inspect the post-doping waferOptical microscope□ Done __________ | Inspect gate edges, island gaps, residue and source-film defect signatures. Compare against the pre-SOD map before covering the device with ILD.
Check No visible bridge, film loss or source residue outside the bound defect limits. Record Defect map and disposition | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
Order · interlayer dielectric and contact openings
CUSTOMER-ORDER PROCESSThe ILD is part of the four-mask production target. It permits useful routing over gates and active silicon while contacts expose only deliberate landings.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N037Clean for interlayer dielectric depositionBound post-SOD pre-PECVD wet clean□ Done __________ | Run the cleaning sequence accepted by the selected ILD chamber for the full SOD and metrology history. Keep the native/thermal-oxide loss within the binding.
Check Surface free of source residue and organics; history accepted by the chosen chamber. Record Clean recipe and queue to deposition | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N038Deposit the interlayer oxidePECVD3 · bound accepted chamber/program□ Done __________ | Deposit the selected oxide continuously over gate tops, sidewalls and S/D. Include a thickness/stress witness in the same run.
Check Measured coverage and minimum insulating thickness are sufficient at mesa/gate edges; no pinholes or cracks in the qualified film. PECVD is not assumed perfectly conformal. Record Recipe, trace, witness and chamber history | PECVD / finite step coverage PECVD covers tops, steps and sidewalls with finite, recipe-dependent step coverage. Rounded contours show intended insulation; pinholes, seams and thin corners require witness checks. |
| N039Measure the ILD witnessEllipsometry / film-stress metrology□ Done __________ | Map thickness and inspect stress/cracks on the matching witness. Preserve device wafers for contact lithography.
Check Thickness and step coverage inside the qualified window. Record Thickness map and stress/inspection data | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N040Coat M3 CONTACT resistSVGCOAT6□ Done __________ | Run the bound prime/coat/soft-bake program over ILD.
Check Uniform resist at gate and mesa steps, with no edge-bead interference. Record Program and film | Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell. |
| N041Expose M3 CONTACTMLA150□ Done __________ | Align contact holes to the gate landing and S/D windows. Place gate contacts on widened poly above BOX, and keep S/D holes enclosed inside the doped mesa areas.
Check Each opening lands entirely on its intended conductor after worst-case overlay and etch bias. Record Alignment/dose/focus and mask hash | Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit. |
| N042Develop M3 CONTACTSVGDEV6□ Done __________ | Run the bound PEB/develop/rinse/dry cycle.
Check Contact bottoms cleared of resist; no unintended holes. Record Program and actual timing | Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result. |
| N043Inspect contact lithographyOptical microscope / CD metrology□ Done __________ | Measure holes, gate-pad enclosure and spacing from gate/mesa edges before dielectric etch.
Check No contact overlaps a gate sidewall or falls outside the n+ landing. Record Contact CD/overlay and photos | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N044Etch contact oxideCentura MxP · if full history accepted□ Done __________ | Open the ILD using the bound oxide recipe and calibrated clear margin. Account for differing topography and any thin interfacial oxide on S/D/poly.
Check All contacts clear without consuming the n+ depth or gate-poly thickness budget. Record Endpoint/time, recess witness and inspection | Directional plasma contact etch Directional plasma etching removes exposed horizontal film and produces approximately vertical patterned edges. Lateral bias, selectivity and any sidewall residue remain recipe dependent. The oxide contact openings are plasma-etched; the earlier wet gate-oxide clear has a different lateral profile. |
| N045Strip contact resist and fluorocarbon residueMatrix asher · accepted CFx-removal program□ Done __________ | Run the required plasma sequence for the contact-etch residue and full resist strip. Do not replace fluorocarbon removal with an unqualified solvent soak.
Check Contact bottoms and sidewalls free of polymer; no excessive oxidation/recess. Record Recipe/time and residue monitor | Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss. |
| N046Clean the opened contactsBound pre-metal wet clean□ Done __________ | Remove residual organics using the accepted post-contact clean before the final native-oxide clear. Preserve the ILD profile and gate-edge oxide.
Check No polymer or particles in contact chains. Record Clean and oxide-loss records | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N047Inspect contact openingsOptical inspection / sacrificial cross-section witness□ Done __________ | Inspect device openings optically and use the qualification witness to verify bottom clearing, taper and maximum recess.
Check Contact process passes before blanket metal hides the interface. Record Images, profile witness and recess budget | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
Order · aluminum interconnect and finish
CUSTOMER-ORDER PROCESSOne metal layer crosses the gate only over intact ILD. Every crossing and contact type has a monitor in the scribe/test region.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N048Remove native oxide immediately before metalBound contact preclean station□ Done __________ | Run the minimum calibrated final oxide removal on opened Si/poly contacts, rinse/dry and transfer promptly. Include this removal in the contact-recess/ILD-undercut budget.
Check Contact bottoms clean while ILD undercut and gate-edge retreat remain acceptable. Record Actual time, bath and transfer delay | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N049Deposit aluminum–silicon interconnectMRC944 · bound history-compatible route□ Done __________ | Load the accepted carrier, run only the calibrated contact preclean, and sputter the aluminum–silicon film. Deposit on a witness with a defined thickness step.
Check Contact bottom coverage and maximum film temperature within the qualified process; no uncalibrated sputter-clean dose. Record Power/pressure/passes/speed, preclean dose and thickness witness | Sputter deposition / finite coverage Sputtered metal reaches horizontal surfaces and some sidewalls, with reduced coverage at steep or shadowed edges. Contacts are coated surfaces, not solid filled plugs; continuity requires measurement. |
| N050Measure metal thicknessProfilometer / optical inspection · witness□ Done __________ | Measure the defined witness step and inspect film continuity and roughness. Keep stylus marks away from device pads.
Check No discontinuous film at qualified contact/mesa topography. Record Thickness trace and film photos | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N051Coat and cure the protective BARCSVGCOAT3 / bound AR3 program□ Done __________ | Coat and cure the qualified bottom antireflective coating over aluminum before positive-resist processing. It also isolates Al from TMAH-containing developer.
Check Continuous insoluble BARC over Al; correct cure and no exposed Al in the lithography region. Record BARC program, film thickness and cure barc · sputter · morph-spin | Spin coating / cured BARC Spin-coated BARC partly levels the metal topography and is then cured. It can be thinner at convex edges and thicker in recesses; the drawing does not imply a uniform conformal film. |
| N052Coat M4 METAL resistSVGCOAT6□ Done __________ | Use the qualified metal/BARC-stack lithography program with 2 µm MiR701 coat and soft bake.
Check Continuous resist at metal steps and correct edge bead removal. Record Program, thickness and coat defects | Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell. |
| N053Expose M4 METALMLA150□ Done __________ | Align and expose metal to remove. Retain the designed wires/pads and metal enclosure around all contacts; route crossover conductors only over intact ILD.
Check No accidental gate/source/drain join in the mask; no open contact lacking metal enclosure. Record Alignment, dose/focus and mask hash | Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit. |
| N054Develop M4 METALSVGDEV6□ Done __________ | Run the bound metal lithography PEB/develop/rinse/dry sequence.
Check Metal-clear regions free of resist and retained wires/pads continuous. Record Program and timing | Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result. |
| N055Inspect metal resistOptical microscope / CD metrology□ Done __________ | Check minimum spaces, contact enclosure, crossover locations, pad openings and routing around mesa steps.
Check Resist pattern matches connectivity and dimensional requirements. Record CD/overlay photos and defects | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N056Open BARC through the metal resist maskN-BARC selected metal-compatible plasma tool□ Done __________ | Remove BARC only in the developed resist openings using the bound masked O₂ program. Preserve enough resist and the required dimensions for aluminum etching.
Check BARC clears in metal-removal regions; protected wires and pads remain masked and Al is not measurably corroded. Record Tool/recipe/time and clear/CD witness | Patterned plasma BARC opening Plasma clears BARC through the developed resist openings. Actual lateral BARC loss and resist erosion depend on the bound plasma program; the illustration does not assign a calibrated etch slope. |
| N057Harden the metal-etch maskAxcelis UV hard bake□ Done __________ | Run the current program appropriate for MiR701 and 150 mm loading before LAM7. Use the complete loaded program rather than reconstructing separate lamp/temperature columns.
Check No resist reticulation or unacceptable CD change; wafer backside clean for the etcher. Record Program and before/after critical CD | Resist hardening The patterned resist is hardened for etching. The mask stays in place; any bake-induced rounding or profile change must remain inside the lithography/etch budget. |
| N058Etch aluminum interconnectLAM7□ Done __________ | Run the bound Al–Si etch and calibrated clear margin; clear metal at gate and mesa steps. Arrange the immediate corrosion-control path before unloading.
Check No metal stringers connecting isolated nets; remaining ILD still meets crossover isolation. Record Recipe, etch trace and overetch | Directional plasma metal etch Directional plasma etching removes exposed horizontal film and produces approximately vertical patterned edges. Lateral bias, selectivity and any sidewall residue remain recipe dependent. |
| N059Remove post-etch chlorine and resist promptlyMatrix / bound corrosion-control transfer□ Done __________ | Follow the current LAM7-to-strip transfer sequence without an unplanned queue. Remove hardened resist, remaining BARC and chlorine-bearing residues through the accepted program.
Check No prolonged untreated air exposure or visible chloride corrosion. Record Time out of etcher, time into strip and program | Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss. |
| N060Clean the patterned metalMSINK1 if eligible; otherwise N-ROUTE metal-clean station□ Done __________ | Use the bound metal-compatible solvent/clean/rinse/dry route. Do not return Al wafers to oxidizing MOS acid cleans. MSINK1 is unavailable after any MSINK16/18 history.
Check No residual resist, corrosion, stains or loose metal. Record Clean/rinse/dry record | Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget. |
| N061Inspect interconnect and contactsOptical microscope□ Done __________ | Inspect device pads, gate crossovers, mesa feet, metal combs and serpentines. Use a sacrificial cross-section or tilted SEM witness for first qualification of contact coverage.
Check No bridges, opens, pinholes or coating discontinuities outside N-RELEASE. Record Defect map and representative images | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N062Run the bound post-metal annealN-FINISH selected metal-compatible anneal tool□ Done __________ | Run the qualified contact/interface treatment for this completed SOD/PECVD/Al history. Use paired monitors to retain an as-deposited comparison during qualification.
Check Contacts improve or remain stable without increased leakage, metal interaction or film damage. Record Complete thermal trace and pre/post witness IDs | Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step. |
Order · electrical test and die release
CUSTOMER-ORDER PROCESSThese are actual measurement visits or instrument setups. Criteria apply to a declared operating envelope and do not assume an ohmic body connection.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N063Set up wafer probing and verify wiringEverbeing EB-8 / selected analyzer□ Done __________ | Load the wafer using the defined handle/chuck condition. Verify channel-to-tip connections, current floor and compliance with a known resistor and open circuit.
Check No claim that chuck bias equals transistor body bias; current-floor and cable leakage adequate for release tests. Record Instrument/configuration and baseline leakage | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N064Measure contacts and interconnect monitorsEB-8 / four-terminal instrumentation□ Done __________ | Measure TLM/Kelvin contacts, n+ and poly chains, metal serpentines and open/short combs. Use low-bias bidirectional I–V before applying operating voltages.
Check Contacts approximately linear and stable within the application range; contact resistance is not confused with sheet resistance. Record Raw I–V, extracted Rc/Rs and failure map | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N065Screen gate and isolation leakageEB-8 / analyzer□ Done __________ | Short S and D together for a defined gate-leakage measurement, then test inter-island and gate-crossing monitors. Increase bias only while below compliance.
Check No gate/crossover breakdown or inter-island conduction. Discard compliance-limited points from device extraction. Record IG/IS/ID and isolation curves | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N066Measure low-drain transfer curvesEB-8 / analyzer□ Done __________ | Measure forward/reverse gate sweeps on the L/W and wafer-position matrix. Use a logged rest and repeat under identical illumination and timing.
Check Enhancement-mode behavior and acceptable threshold/SS distributions; no extraction from moving contacts or current compliance. Record Raw curves, Vt method, SS, Ion/Ioff and timing | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N067Measure output and floating-body behaviorEB-8 / analyzer; pulse equipment if available□ Done __________ | Acquire output curves at several gates, beginning at small drain voltage. Repeat after logged off/on bias histories and compare pulsed versus DC measurements during qualification.
Check Measured history effects fit the model and released voltage/temperature envelope; body tying is not used as an undocumented explanation. Record Output/history/pulse data and compact-model revision | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N068Test circuit primitivesProbe station / oscilloscope / supply□ Done __________ | Test the mask’s enhancement-load or externally loaded NMOS inverter and a compatible oscillator. Measure transfer characteristic, logic levels, gain, delay and static supply current.
Check Noise margins and static-power behavior support the intended circuit class; oscillator activity alone is insufficient. Record Waveforms, DC transfer, load, supply current and pass map | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N069Complete the wafer test mapProbe station / data station□ Done __________ | Run the released wafer-position and device-geometry sample plan, record every tested failure and assign die dispositions. Save all raw measurements before singulation.
Check Only dies meeting the declared model and operating envelope advance to shipment. Record Yield denominator, bin map, data hashes and test-end timestamp | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
Order · singulate and package bare research die
CUSTOMER-ORDER PROCESSThe 24-hour objective includes these operations. No passivation, package assembly or ESD rating is implied by the four-mask process.
| Visit / destination | Operation, settings and check | Wafer after this visit |
|---|---|---|
| N070Apply dicing protectionN-FINISH accepted coat station□ Done __________ | Apply the qualified temporary protective coating to the front surface, keeping the dicing mount and later removal compatible with exposed Al and pads.
Check Pads and fragile features protected; no unqualified bake or contamination route. Record Coating/program and wafer ID | Spin coating / dicing protection The temporary protective coating partly levels the completed metal relief. The drawing assumes the bound dicing-protection coat/bake has ended; its liquid-flow profile is qualitative. |
| N071Mount and dice the waferN-FINISH accepted dicing saw□ Done __________ | Mount using the qualified carrier/tape and cut the released streets with the documented blade and feed program. Preserve the die map orientation.
Check No cuts encroach on devices; edge chipping and delamination within release limits. Record Saw program, mount and die map | Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step. |
| N072Remove dicing protection and dryN-FINISH metal-compatible die-clean station□ Done __________ | Remove the temporary coating and saw debris using the qualified Al-compatible sequence, rinse/dry as specified, and retain die identity.
Check No stains, residue, pad damage or mobile particles. Record Clean/dry record and die IDs | Remove dicing protection The temporary protection is stripped from the singulated die, exposing the existing metal/ILD surface. No permanent passivation is added. |
| N073Inspect and retest singulated diesDie microscope / final-test fixture□ Done __________ | Inspect edges and pads, and retest the defined continuity/leakage/function subset after dicing. Compare with wafer-probe bins.
Check No new leakage, open interconnect or dicing-induced failure. Record Final die bins and images | Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result. |
| N074Pack and release the research diesClean ESD-controlled packing station□ Done __________ | Place passing dies into the qualified carrier with orientation and handling information. Attach the electrical envelope, lot/model revision and test results.
Check Count and identity match the final map; shipment claims match the demonstrated process and actual elapsed time. Record Carrier ID, die count, release record and timestamps | Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step. |
Completion criteria
- Establish the device-silicon/BOX maps, oxide thickness/loss, gate CD, mesa isolation, sidewall cleanliness and metal coverage on qualification lots. The approximately 187 nm silicon remaining after nominal gate oxidation is near a depletion crossover for the proposed doping; label devices by measured behavior, not an assumed PD or FD classification.
- Qualify phosphorus activation in single-crystal silicon and poly independently. A depth/profile witness and the total contact recess/metal-interaction budget must support the chosen contact module. Sheet resistance alone does not prove junction depth or adequate poly doping at the dielectric interface.
- Suggested initial electrical development gates at 3.3 V: enhancement operation with Vt initially targeted within 0.3–1.2 V; Ion/Ioff ≥10⁴ on offered geometries; IG ≤1 nA per transistor and ≤10⁻⁴ Ion, subject to instrument floor; contact drop <5% of total on-state voltage drop. Freeze final limits after measured distributions and models exist.
- Require repeatable transfer/output curves, mesa-edge controls, inter-island isolation, Kelvin/TLM contacts, poly/metal chains, interconnect combs, and an NMOS inverter plus oscillator designed for the actual enhancement-only library. A functioning oscillator is not a substitute for leakage, noise-margin or yield evidence.
- Measure floating-body hysteresis, rest/bias history, high-drain kink and pulsed-versus-DC behavior at the intended temperature and voltage limits. Either constrain the product’s envelope and compact model to the results or revise the device; a nonexistent body tie cannot be assumed in simulation.
- Count passing dies against all fabricated/testable dies using a documented sampling and retest rule. Establish repeatability across independent lots and storage ages. This document supplies no demonstrated yield or demonstrated sub-24-hour turnaround.
- The four-mask endpoint is unpassivated bare research die. Packaged-product reliability, humidity protection, ESD ratings and general-purpose analog/body-bias capability are not silently included. Additional passivation/pad opening or body-contact modules change the mask count and schedule.
Process references and source notes
- materials NanoLab materials control and compatibility
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- coat SVGCOAT6 resist coating
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- develop SVGDEV6 resist development
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- mla MLA150 direct-write lithography
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- lam8 LAM8 silicon and poly etch
Official primary manual text re-read on 21 September 2026 from a downloaded Google Docs text export. Tool capability/material rules and recipe references are documented; this integrated wafer history and film-specific recipe still require the named bindings.
- wet6 MSINK6 MOS clean
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- wet7 MSINK7 oxide etch
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- wet8 MSINK8 post-resist clean
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- wet1 NanoLab equipment manual index — MSINK1 metal clean
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- tystar1 Tystar1 gate oxidation
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- tystar10 Tystar10 LPCVD polysilicon
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- headway Headway1 coating
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- rtp RTP3 rapid thermal processing
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- matrix Matrix plasma resist strip
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- pecvd3 Oxford PECVD3
Official primary manual text re-read on 21 September 2026 from a downloaded Google Docs text export. Tool capability/material rules and recipe references are documented; this integrated wafer history and film-specific recipe still require the named bindings.
- mxp Centura MxP oxide etch
Official primary manual text re-read on 21 September 2026 from a downloaded Google Docs text export. Tool capability/material rules and recipe references are documented; this integrated wafer history and film-specific recipe still require the named bindings.
- sputter MRC944 aluminum–silicon sputter
Official primary manual text re-read on 21 September 2026 from a downloaded Google Docs text export. Tool capability/material rules and recipe references are documented; this integrated wafer history and film-specific recipe still require the named bindings.
- lam7 LAM7 aluminum etch
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- hardbake Axcelis UV hard bake
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- barc SVGCOAT3 BARC coating
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- semi SEMI contact-window etch — case-reviewed route alternative
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- sinter Tystar18 aluminum sinter — eligibility-dependent reference
Official primary manual text re-read on 21 September 2026 from a downloaded Google Docs text export. Tool capability/material rules and recipe references are documented; this integrated wafer history and film-specific recipe still require the named bindings.
- probe Everbeing EB-8 electrical probing
Historical primary-manual reference retained from the earlier Berkeley traveler. Linked Google document could not be re-read in this revision; actual loaded program and wafer-history acceptance must be bound before execution.
- sod Filmtronics spin-on diffusants
Manufacturer product-family information verified in this revision; no bottle-specific dispense/cure/diffusion recipe supplied by this page.
- sodpaper Normann et al. — shallow phosphorus emitters by RTP
Earlier traveler cites P509 RTP experiments at 900–950°C and tens of seconds on bulk silicon. Full source was not re-accessible in this revision; no SOI diffusion depth or poly activation is inferred.
- hu5 Chenming Hu — MOS capacitor electrostatics
Primary technical source; supports the cited mechanism or module, not qualification of this proposed integrated traveler.
- hu7 Chenming Hu — MOSFET scaling, leakage and SOI
Primary technical source; supports the cited mechanism or module, not qualification of this proposed integrated traveler.
- contact MIT 6.720J — metal–semiconductor contacts
Primary technical source; supports the cited mechanism or module, not qualification of this proposed integrated traveler.
- morph-spin MicroChemicals: spin coating over textured substrates
PDF pp. 1 and 4 explain edge pullback and accumulation in holes/spaces. Direct evidence for resist morphology; analogous leveling shown for SOD is a qualitative liquid-flow inference, not measured coverage for a chosen dopant formulation.
- morph-fab Chenming Hu: Device Fabrication Technology, chapter 3
PDF pp. 3–5 and 10–12 support silicon-consuming thermal oxidation, lateral wet-etch retreat and directional plasma etching. The diagrams do not assign calibrated etch angles, undercuts or diffusion lengths.
- morph-deposit MEMS Exchange: deposition processes and step coverage
Explains CVD/PVD step-coverage differences and silicon consumption during oxidation. LPCVD wrap, finite PECVD coverage, directional evaporation and reduced PVD sidewall coverage are qualitative morphology conventions.
- morph-etch MEMS Exchange: isotropic and anisotropic etching
Distinguishes isotropic lateral undercut, crystallographic wet etching and directional RIE. The mesa route here is directional plasma etching, not a KOH crystal-plane etch.