PROCESS DEVELOPMENT · CLEANROOM TRAVELER

Experimental NMOS · polysilicon ring gates

Supplied oxide / poly stack · first transistor screen after one lithography level

This bulk-silicon development flow starts with a supplied 30 nm gate oxide / 150 nm undoped polysilicon stack. The first mask defines isolated ring gates and source/drain windows; one phosphorus SOD operation dopes the exposed silicon and the gate poly so the large ring devices can be screened before contacts or wiring are fabricated.

The same wafer can then progress through conventional-gate isolation and body windows, 400 nm interlayer oxide, contact openings and 500 nm Al–2%Si wiring. The progression separates gate/doping problems from later contact and interconnect problems and preserves working large rings as controls for the smaller devices.

Four lithography levels complete the experiment; stack manufacture is outside this traveler. Directly probed stages have a floating body, and the late metal-on-p-Si body landing is only a candidate contact until measured. Numerical tool recipes are references with the lot-specific settings bound below; this is a development sequence rather than a released production process.

Incoming wafer: 150 mm prime p-Si (100), 675 ±25 µm; 0.5–1 Ω·cm baseline, actual lot recorded
Incoming films: 30 nm thermal SiO₂ + 150 nm undoped LPCVD poly; backside state recorded
Lithography: P1 rings/windows; P2 gate cuts/body windows; P3 contacts; P4 metal
Final films: 400 nm PECVD SiO₂; 500 nm sputtered Al–2%Si
First useful endpoint: Ring-device test after P1 and phosphorus SOD; no gate-stack furnace preparation here

Lot / wafers ____________________Operator ____________________Date ____________________

Step explorer

Listed sequence ↓

1 / 69

Device Section Drag to rotate · scroll to zoom Cut at section

Inspection / measurement

The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

3D process structure

Through ring centre

Silicon body / handlen+ siliconThermal SiO₂ / BOXPolysilicon gateInterlayer dielectricPhotoresistBARC underlayerPhosphorus spin-on sourceAluminum metallization

Sections are cut from the same 3D material geometry. Film thickness, etch bias and diffusion lengths are exaggerated; coverage must be verified on the actual wafer.

Geometry and coverage

Cross-sections are after each visit, qualitatively drawn and vertically exaggerated. The supplied frontside oxide/poly stack is already present at the first step. The ring center cut crosses outer source, gate, inner drain, gate and outer source. The gate contact tab lies away from the active gate oxide to reduce probe damage. After P1 the ring is isolated but conventional comparator gates can remain part of surrounding poly until P2 cuts them free. The diagrams do not imply functional conventional devices before that cut. Dopant boundaries are illustrative; sheet resistance alone does not establish the lateral/depth profile. No chuck or backside contact is assumed ohmic. P2 body windows expose the original p-type substrate after phosphorus doping. There is no p+ body implant/diffusion in this experiment, so final body-contact quality is measured explicitly. Morphology is illustrative rather than a dimensional prediction: directional plasma etches have steep walls, wet oxide etches retreat laterally, thermal oxidation consumes silicon, and deposited films follow their stated deposition method. Numerical geometry is deliberately exaggerated for legibility. Spin-on resist, BARC and dopant source films wet accessible relief and partially level it. Convex corners may be thin and recesses thick; a smooth drawing is the intended coverage, not evidence of pinhole-free coating. Wet, baked and thermally converted source states are distinguished.

Receive the supplied oxide / poly stack

P001 · Inspect incoming coated wafers

Inspect front, edge and backside of the supplied oxide/poly wafers. Identify device wafers, oxide-only witnesses and a matched poly witness; retain the supplier run record.

Go to this visit in the run sheet ↓

Lot recipe assignments

Use these assignments wherever their IDs appear in the sequence. Complete the values before starting the affected module.

Assignment	Value for this lot	Context
STACK Incoming stack / film limits	Oxide 30 nm ±10%; poly 150 nm ±10 nm requested; actual incoming map ___	Use supplier oxide-only monitors to constrain the optical fit. These are procurement targets, not measured values. Backside retained/stripped ___; no film growth is included here.
LITHO Exposure recipes	P1–P4 dose/focus or contact mode ___; writer/aligner ___; mask edge budgets ___	Baseline coat/develop references are specified in the visits. The existing MA8 route may be transferred to MLA150 with calibrated dose/focus and tone.
OX-ETCH Oxide opening and native-oxide clean	Bath/rate ___; P1 clear ___ s; P2 clear ___ s; native-oxide dips ___	Use actual remaining oxide thickness; include lateral gate-edge undercut and every later glass/precontact strip.
P-SOD Phosphorus coat / cure / thermal module	Product/bottle ___; spinner ___; rpm/time/thickness ___; cure ___; thermal tool ___; peak ___ °C / ___ s; ambient/ramp/carrier ___	The same cycle must produce acceptable n+ silicon and conductive poly at its oxide interface. RTP3 source-present acceptance is not inferred from its availability.
P-STRIP Source glass removal	Bench ___; bath ___; measured rate ___; clear time ___; permitted gate-edge oxide loss ___	Remove all source and interfacial residue with a demonstrated oxide-loss budget.
RETURN Post-SOD / probe history	Cleaning station/chemistry ___; carriers/SRD ___; permitted etchers/coaters/deposition tools ___	No automatic MOS re-entry after non-MOS RTP or probe contact. If early-probed wafers cannot re-enter downstream tools, use a sacrificial pilot plus an unprobed matched continuation wafer.
ILD Interlayer dielectric	History-compatible PECVD tool ___; 400 nm SiO₂ recipe ___; ___ °C / ___ W / ___ mTorr; flows/rate ___	PECVD3 generally requires MSINK6-cleaned Si and is not assumed eligible here. PECVD4 is a candidate with a different contamination environment; its use still needs the complete RETURN route.
CONTACT Contact etch and premetal clean	Actual ILD clear/overetch ___; native-oxide dip ___; sputter preclean ___	Clear both poly and silicon landing heights. CFx etch residue goes to plasma strip/EKC265, not straight to a communal 1165 bath.
AL Blanket Al–Si and lithography	MRC944 current recipe ___; ≤3000 W Al–Si target; passes/speed ___; BARC program ___; BARC-open recipe ___; metal etch/endpoints ___; corrosion-control route ___	500 nm Al–2%Si. No resist enters MRC944. Keep BARC between Al and TMAH developer; do not copy obsolete 4 kW examples.
TEST Electrical limits	Gate maximum ___ V; gate-leakage criterion ___; device current ranges ___	Initial ID compliance 10 µA and IG compliance 10 nA are protective starting values; record and exclude compliance-limited points from extraction.
ANNEAL Optional contact-anneal split	N/A unless selected: compatible tool ___; ___ °C / ___ min; ambient ___; clean ___	Measure as-deposited devices first. Tystar18 is MOS-only; RTP3 is not a substitute for a long furnace sinter.

Cleanroom sequence

69 visits

Each numbered visit follows the wafer to a tool, bench or measurement station. The section at right shows the intended structure after that visit.

Silicon body / handlen+ siliconThermal SiO₂ / BOXPolysilicon gateInterlayer dielectricPhotoresistBARC underlayerPhosphorus spin-on sourceAluminum metallization

Receive the supplied oxide / poly stack

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
P001Inspect incoming coated wafersuvscope□ Done __________	Inspect front, edge and backside of the supplied oxide/poly wafers. Identify device wafers, oxide-only witnesses and a matched poly witness; retain the supplier run record. Stack 30 nm thermal SiO₂ / 150 nm undoped poly Substrate 150 mm p-Si (100), 675 ±25 µm; 0.5–1 Ω·cm baseline Backside Record retained oxide/poly or supplier-stripped condition Check No fractures, gross particles, film peeling or unknown tape/resist history. Backside contact is not assumed electrical. Record Wafer/lot IDs ___; actual resistivity ___; backside ___ index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P002Map incoming filmsellips2 / nanoduv□ Done __________	Map the coated stack and oxide-only supplier witness; constrain the multilayer optical fit using the independent oxide result. Map Center plus four radial sites Nominal films 30 nm oxide; 150 nm undoped poly Check Film values and fit quality are consistent with STACK; do not confuse poly optical-fit uncertainty with oxide variation. Record tOX ___ nm; tPOLY ___ nm; map/range ___ index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Visit / destination

Operation, settings and check

Wafer after this visit

P001Inspect incoming coated wafersuvscope□ Done __________

Inspect front, edge and backside of the supplied oxide/poly wafers. Identify device wafers, oxide-only witnesses and a matched poly witness; retain the supplier run record.

Stack: 30 nm thermal SiO₂ / 150 nm undoped poly
Substrate: 150 mm p-Si (100), 675 ±25 µm; 0.5–1 Ω·cm baseline
Backside: Record retained oxide/poly or supplier-stripped condition

Check No fractures, gross particles, film peeling or unknown tape/resist history. Backside contact is not assumed electrical.

Record Wafer/lot IDs ___; actual resistivity ___; backside ___

index

Ring gate

Conventional gate

Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

P002Map incoming filmsellips2 / nanoduv□ Done __________

Map the coated stack and oxide-only supplier witness; constrain the multilayer optical fit using the independent oxide result.

Map: Center plus four radial sites
Nominal films: 30 nm oxide; 150 nm undoped poly

Check Film values and fit quality are consistent with STACK; do not confuse poly optical-fit uncertainty with oxide variation.

Record tOX ___ nm; tPOLY ___ nm; map/range ___

index

Ring gate

Conventional gate

P1 · ring gates and diffusion openings

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
P003Organic clean and rinsemsink8□ Done __________	Remove organic residue at MSINK8, then complete the full QDR before the subsequent MOS-clean visit. Preserve the gate oxide; only the pre-SOD, eligible wafer history uses this route. Bath Piranha · 120°C · 10 min Transfer Piranha → QDR; preserve the gate oxide Check No residual resist enters the clean baths; preserve the lot’s oxide-loss budget. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P004Surface clean and rinsemsink6□ Done __________	Clean the supplied coated wafer through the oxide-preserving MOS-clean sequence after MSINK8. Omit HF to preserve the incoming gate oxide. Sequence Piranha → QDR → 0.1% HCl → QDR Baths Piranha 120°C, 1–5 min; HCl room temperature, 1 min Rinse QDR >10 MΩ·cm Check This is before the non-MOS SOD/probe history boundary. cleanmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P005Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Record the actual recipe and any departure from the bound lot settings. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P006Coat Mask 1 resistsvgcoat6□ Done __________	Load the coat track for the complete prime, coat, edge-bead removal and soft-bake cycle. Film MiR 701 · 2 µm Coat HMDS module 100°C; 900 rpm nominal final spin Bake 90°C · 90 s, inside the track cycle Program 01_MiR701_2.0um_Bake90C90s Check Uniform resist and clean backside; execute the track program as one tool visit. coat · morph-spin	Ring gate Conventional gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
P007Expose Mask 1ksaligner · MA8□ Done __________	Orient P1 to the wafer flat and expose the ring gates, S/D openings and alignment marks. Exposure LITHO dose, intensity/focus and alignment mode for this level Baseline MA8 365/436 nm configuration; exposure time = calibrated dose / measured intensity Check Check mask identity, orientation, tone and overlay before exposure; retain alignment-mark images. aligner	Ring gate Conventional gate Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
P008Develop Mask 1svgdev6□ Done __________	Run the complete post-exposure bake, development, DI rinse and dry cycle. Program 01_PEB110C90s_MF26A60s PEB 110°C · 90 s Developer MF-26A · 60 s Check Developed openings are clear; no unintended bridges or pinholes. develop	Ring gate Conventional gate Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
P009Inspect Mask 1uvscope□ Done __________	Check ring closure, gate tabs and their isolation moats, conventional S/D openings and alignment marks before etching. Sample Center, mid-radius and edge; save representative images Check Save site-matched photographs and measured critical dimensions; resolve visible defects before the next irreversible etch/deposition. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P010Harden Mask 1 resistaxcelis□ Done __________	Move to the UV hard-bake tool and run the complete MiR701 thermal/lamp program before etching. Reference MiR701 program U; exact loaded thermal/UV program in LITHO Check Printed edges remain intact; enough resist remains for the following etch. harden	Ring gate Conventional gate Resist hardening The patterned resist is hardened for etching. The mask stays in place; any bake-induced rounding or profile change must remain inside the lithography/etch budget.
P011Etch Mask 1 polysiliconlam8□ Done __________	Run one 8003 breakthrough, main-etch and overetch sequence to clear the 150 nm poly and stop on thermal oxide. Breakthrough CF₄ 100 sccm; 13 mTorr; TCP/bias 200/40 W; 10 s Main Cl₂/HBr 50/150 sccm; 12 mTorr; TCP/bias 300/150 W; endpoint A Overetch HBr/O₂/He 100/1/100 sccm; 80 mTorr; TCP/bias 200/150 W; 20% of main etch Check Endpoint trace is saved; gate oxide remains intact. Thin-poly clear time is calibrated rather than copied from a nominal etch rate. Record Recipe/endpoint ___; main/OE times ___ polyetch · history · morph-etch	Ring gate Conventional gate Directional plasma poly etch Directional plasma etching removes exposed horizontal film and produces approximately vertical patterned edges. Lateral bias, selectivity and any sidewall residue remain recipe dependent. Mask 1 isolates the ring; the conventional comparator can still connect to field poly until Mask 2.
P012Etch Mask 1 oxide; rinsemsink7□ Done __________	Etch the exposed thermal oxide through the resist mask, then transfer immediately to QDR. Preserve the oxide beneath the gate. Film Actual remaining thermal oxide; 30 nm nominal incoming Etch OX-ETCH chemistry, measured rate and clear margin Rinse Full MSINK7 QDR; historical four fill/dump cycles Check Silicon exposed only in intended windows; oxide undercut remains within the edge budget. wetoxide · morph-etch	Ring gate Conventional gate Isotropic wet oxide etch Wet etching clears the exposed oxide and retreats laterally under adjacent resist/poly edges. Retained gate oxide protects the channel only within the measured undercut budget.
P013Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Full compatible rinse/dry cycle; no watermarks, residual liquid or backside deposits. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P014Strip resistMatrix · RETURN-qualified history after SOD/probing□ Done __________	Run the full oxygen-plasma strip to remove resist and etch residue. Settings 3.75 Torr; O₂ MFC1 40%; 400 W; 250°C Time 2.5 min starting strip for ~2 µm resist; total ______ min to clear Check Resist is fully cleared, including etch residue. Confirm any additional wet residue clean from the bound route. ash	Ring gate Conventional gate Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
P015Inspect the etched openingsuvscope□ Done __________	Inspect the cleared S/D silicon, gate edges, ring moats and alignment marks. Measure printed gate widths and opening sizes. Sample Center, mid-radius and edge; save representative images Check Save site-matched photographs and measured critical dimensions; resolve visible defects before the next irreversible etch/deposition. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Phosphorus SOD and first ring-device screen

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
P016Organic clean and rinsemsink8□ Done __________	Remove organic residue at MSINK8, then complete the full QDR before the subsequent MOS-clean visit. Preserve the gate oxide; only the pre-SOD, eligible wafer history uses this route. Bath Piranha · 120°C · 10 min Transfer Piranha → QDR; preserve the gate oxide Check No residual resist enters the clean baths; preserve the lot’s oxide-loss budget. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P017Surface clean and rinsemsink6□ Done __________	Complete the pre-SOD clean on the still-eligible patterned wafer, then the brief native-oxide dip specified by OX-ETCH and the full rinse. The thin gate-edge oxide must survive this exposure. Sequence Piranha → QDR → dilute HCl → QDR → bound final HF → QDR Historical reference Piranha 120°C, 1–5 min; HCl 0.1%, room temperature, 1 min Native-oxide removal OX-ETCH chemistry/time; measured gate-edge oxide loss Check No residual organics; exposed S/D and poly surfaces match the P-SOD surface-preparation requirement. cleanmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P018Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Full compatible rinse/dry cycle; no watermarks, residual liquid or backside deposits. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P019Spin phosphorus dopantHeadway1 / assigned SOD spinner□ Done __________	Transfer promptly from the clean/dry sequence. Coat the exposed silicon and remaining poly with the phosphorus spin-on dopant; keep the backside and edge clean. Product / coat P-SOD bottle, dispense, rpm, duration and film thickness Check Uniform source coating; no forbidden backside or edge deposits. spin · morph-spin	Ring gate Conventional gate Spin coating / wet dopant source The wet spin-on source reaches accessible tops and sidewalls and can gather at low corners. Its partly leveled profile is illustrative; actual wetting and corner thickness depend on the selected formulation.
P020Cure the dopant filmAssigned exhausted SOD hotplate / oven□ Done __________	Move the coated wafer to the product-specific solvent-cure station, then cool for RTP loading. Cure P-SOD product-specific temperature, time and ambient Check Cure complete; source is not cracked or shedding. sod	Ring gate Conventional gate Source cure / dry precursor The cure removes solvent and converts the wet source into the specified dry precursor. Some shrinkage and profile change are expected; the retained coating is not a second deposited layer.
P021Diffuse S/D and dope the poly gateRTP3 candidate / assigned source-present thermal tool□ Done __________	Execute the complete P-SOD purge, ramp, diffusion and cool sequence on device and witnesses. This cycle dopes both exposed source/drain silicon and polysilicon; save the actual temperature trace. Thermal P-SOD peak, hold, ramp, ambient and carrier Sensing Backside oxide/poly and carrier-specific calibration Tool limit RTP3 ≤1100°C; its allowed duration falls with temperature; use the current temperature/time envelope Check Actual thermal cycle matches the recipe; both n+ silicon and poly conductivity must be measured. No direct return to MOS tools is assumed. Record SOD recipe/trace ___ rtp · history · morph-fab	Ring gate Conventional gate Thermal diffusion / source glass Dopant enters exposed silicon in contact with the source and spreads laterally as well as inward. The remaining source is converted glass; colored silicon is a qualitative doped volume, not a concentration contour.
P022Strip dopant glass and rinseAssigned P-STRIP wet bench□ Done __________	Remove the phosphorus glass and surface cap, then transfer to the full QDR rinse. Limit cumulative oxide loss at the gate edges. Strip P-STRIP bath/rate/time and complete QDR Check Source and interfacial residues clear without excessive gate-edge oxide loss. wetoxide · morph-fab	Ring gate Conventional gate Source-glass removal The source glass is removed while the doped silicon remains. Accessible gate-edge oxide and masking oxide may also recede according to the source-specific strip; the final loss requires measurement.
P023Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Full compatible rinse/dry cycle; no watermarks, residual liquid or backside deposits. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P024Measure the n+ witnesscde-resmap · witness only□ Done __________	Measure the bare-Si witness that traveled through the same P-SOD cycle; keep sharp four-point tips off device gate oxide. Result n+ sheet resistance ______ Ω/□; use the correct geometry correction Check Record geometry correction, measurement current, mean and spread. This measurement does not establish gate-poly doping. Record n+ Rs ___ Ω/□; wafer map ___ index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P025Probe the ring devicesprobe-eb8□ Done __________	On designated large rings, measure the poly resistor before landing on source/drain and the remote gate tab. Screen gate current, then repeat forward/reverse transfer sweeps and reseat contacts. Record the probe map before any further processing. Transfer start S=0 V; VD=50 mV; VG 0→1→0 V Extensions 2 / 3.3 V only after leakage screening, within TEST maximum Limits / dwell ID 10 µA and IG 10 nA initially; 25–50 mV steps; 1 s/point Body Floating; mechanical chuck support is not a body terminal Continuation Same wafer only if RETURN covers probe contact; otherwise sacrifice this pilot and continue its unprobed matched wafer Check Repeatable gate control; separately measured n+ and poly resistance; no gate short or irreversible probing damage. Flag compliance-limited points. Record Ring screen / poly Rs ___; probe-site map ___ probe · contacts · history	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

P2 · conventional-gate cuts and body windows

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
P026Clean the probed wafer for continuationAssigned post-SOD / post-probe wet station□ Done __________	Use the oxide-preserving clean and rinse in RETURN for the actual SOD and probe history. Retain the probed-device map and transfer in the dedicated compatible carrier. Route RETURN bench, clean chemistry and rinse; no unbudgeted HF Check No automatic MSINK6 return. The next etch/deposition tool must accept the full history. history · cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P027Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Full compatible rinse/dry cycle; no watermarks, residual liquid or backside deposits. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P028Coat Mask 2 resistsvgcoat6□ Done __________	Load the coat track for the complete prime, coat, edge-bead removal and soft-bake cycle. Film MiR 701 · 2 µm Coat HMDS module 100°C; 900 rpm nominal final spin Bake 90°C · 90 s, inside the track cycle Program 01_MiR701_2.0um_Bake90C90s Check Uniform resist and clean backside; execute the track program as one tool visit. coat · morph-spin	Ring gate Conventional gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
P029Expose Mask 2ksaligner · MA8□ Done __________	Align to the P1 marks. Expose the conventional-gate cuts and p-type body windows; keep all existing n+ S/D openings protected. Exposure LITHO dose, intensity/focus and alignment mode for this level Baseline MA8 365/436 nm configuration; exposure time = calibrated dose / measured intensity Check Existing n+ source/drain windows are completely covered by the mask during poly etch; ring gates and tabs are protected. aligner	Ring gate Conventional gate Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
P030Develop Mask 2svgdev6□ Done __________	Run the complete post-exposure bake, development, DI rinse and dry cycle. Program 01_PEB110C90s_MF26A60s PEB 110°C · 90 s Developer MF-26A · 60 s Check Developed openings are clear; no unintended bridges or pinholes. develop	Ring gate Conventional gate Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result. P2 resist protects the pre-existing n+ windows and retained gates; only the gate-cut and new body-window areas are exposed.
P031Inspect S/D protectionuvscope□ Done __________	Check resist coverage at every S/D boundary, gate end, poly tab and body opening. Measure overlay at two separated marks. Sample Center, mid-radius and edge; save representative images Check Save site-matched photographs and measured critical dimensions; resolve visible defects before the next irreversible etch/deposition. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P032Harden Mask 2 resistaxcelis□ Done __________	Move to the UV hard-bake tool and run the complete MiR701 thermal/lamp program before etching. Reference MiR701 program U; exact loaded thermal/UV program in LITHO Check Printed edges remain intact; enough resist remains for the following etch. harden	Ring gate Conventional gate Resist hardening The patterned resist is hardened for etching. The mask stays in place; any bake-induced rounding or profile change must remain inside the lithography/etch budget.
P033Etch Mask 2 polysiliconLAM8 · only on the bound RETURN route□ Done __________	Run one 8003 breakthrough, main-etch and overetch sequence to clear the 150 nm poly and stop on thermal oxide. Keep all n+ S/D openings covered by resist. The RETURN route must include this etched/probed wafer history; otherwise continue the matched unprobed wafer. Breakthrough CF₄ 100 sccm; 13 mTorr; TCP/bias 200/40 W; 10 s Main Cl₂/HBr 50/150 sccm; 12 mTorr; TCP/bias 300/150 W; endpoint A Overetch HBr/O₂/He 100/1/100 sccm; 80 mTorr; TCP/bias 200/150 W; 20% of main etch Check Endpoint trace is saved; gate oxide remains intact. Thin-poly clear time is calibrated rather than copied from a nominal etch rate. Keep all existing n+ windows covered: LAM8 also etches crystalline silicon. Record Recipe/endpoint ___; main/OE times ___ polyetch · history · morph-etch	Ring gate Conventional gate Directional plasma poly etch Directional plasma etching removes exposed horizontal film and produces approximately vertical patterned edges. Lateral bias, selectivity and any sidewall residue remain recipe dependent. Existing S/D openings stay under resist while the comparator gates are cut free.
P034Etch Mask 2 oxide; rinseMSINK7 only if RETURN eligible / assigned oxide bench□ Done __________	Clear oxide at the new P2 cuts and body windows while protecting existing n+ openings and the ring gates; complete the full rinse. The newly exposed body silicon has no deliberate p+ doping. Film Actual remaining thermal oxide; 30 nm nominal incoming Etch OX-ETCH chemistry, measured rate and clear margin Rinse Full MSINK7 QDR; historical four fill/dump cycles Check Silicon exposed only in intended windows; oxide undercut remains within the edge budget. Full post-SOD/probe history must fit this station. wetoxide · morph-etch	Ring gate Conventional gate Isotropic wet oxide etch Wet etching clears the exposed oxide and retreats laterally under adjacent resist/poly edges. Retained gate oxide protects the channel only within the measured undercut budget. Newly opened body windows expose undoped p-type bulk, not a fabricated p+ contact.
P035Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Full compatible rinse/dry cycle; no watermarks, residual liquid or backside deposits. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P036Strip resistMatrix · RETURN-qualified history after SOD/probing□ Done __________	Run the full oxygen-plasma strip to remove resist and etch residue. Settings 3.75 Torr; O₂ MFC1 40%; 400 W; 250°C Time 2.5 min starting strip for ~2 µm resist; total ______ min to clear Check Resist is fully cleared, including etch residue. Confirm any additional wet residue clean from the bound route. ash	Ring gate Conventional gate Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
P037Probe the conventional devicesprobe-eb8□ Done __________	Inspect the stripped gates in the probe microscope. Probe large conventional comparators and repeat the same ring controls using identical timing and illumination; keep all measurements body-floating. Bias VD=50 mV; same VG range and timing as the first ring screen Initial limits ID 10 µA; IG 10 nA; mark compliance events Data Contact reseat/repeat, gate leakage and ring before/after P2 Check Conventional gates are isolated and rings retain their earlier behavior. Newly exposed p-type windows are not automatically reliable probe body contacts. probe · history	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Interlayer dielectric and P3 contacts

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
P038Clean for interlayer dielectricAssigned post-SOD / post-probe wet station□ Done __________	Use the oxide-preserving clean and rinse in RETURN for the actual SOD and probe history. Retain the probed-device map and transfer in the dedicated compatible carrier. Route RETURN bench, clean chemistry and rinse; no unbudgeted HF Check No automatic MSINK6 return. The next etch/deposition tool must accept the full history. history · cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P039Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Full compatible rinse/dry cycle; no watermarks, residual liquid or backside deposits. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P040Deposit the interlayer oxideHistory-compatible PECVD tool · ILD binding□ Done __________	After the selected chamber clean and seasoning using its dummy wafer, load the device wafer and deposit the ILD oxide. Complete the purge, cooling and unload sequence. Keep all device-film and chamber-clean steps in the same tool visit. Film 400 nm PECVD SiO₂ Recipe ILD temperature, plasma, pressure and gas flows Time 400 nm / current witnessed deposition rate Compatibility PECVD3 is not assumed eligible after RTP3/probing; candidate PECVD4 requires its own RETURN route and contamination assessment PECVD4 candidate reference CH4-STD-SiOx Recipe 1010: 350°C, 1000 mTorr, 81 MHz/200 W; Ar/N₂O/N₂/10%-SiH₄-in-Ar 650/150/200/50 sccm. Use a current measured rate. Check Continuous insulation across gate steps, acceptable particles and no unexpected film cracking. Record Recipe ___; deposition time ___; witness ___ pecvd · history · pecvd4 · morph-deposit	Ring gate Conventional gate PECVD / finite step coverage PECVD covers tops, steps and sidewalls with finite, recipe-dependent step coverage. Rounded contours show intended insulation; pinholes, seams and thin corners require witness checks.
P041Measure the ILDellips2 / nanoduv□ Done __________	Measure the deposited oxide on the witness; map center and edge thickness for the following contact etch. Film 400 nm target; mean ______ nm; range ______ nm Check Map measured thickness and variation for contact clear time; inspect step coverage on matching structures. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P042Coat Mask 3 resistsvgcoat6□ Done __________	Load the coat track for the complete prime, coat, edge-bead removal and soft-bake cycle. Film MiR 701 · 2 µm Coat HMDS module 100°C; 900 rpm nominal final spin Bake 90°C · 90 s, inside the track cycle Program 01_MiR701_2.0um_Bake90C90s Check Uniform resist and clean backside; execute the track program as one tool visit. coat · morph-spin	Ring gate Conventional gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
P043Expose Mask 3ksaligner · MA8□ Done __________	Align P3 to the surviving marks. Expose contacts within the S/D silicon, poly gate tabs and p-type body windows. Exposure LITHO dose, intensity/focus and alignment mode for this level Baseline MA8 365/436 nm configuration; exposure time = calibrated dose / measured intensity Check Check mask identity, orientation, tone and overlay before exposure; retain alignment-mark images. aligner	Ring gate Conventional gate Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
P044Develop Mask 3svgdev6□ Done __________	Run the complete post-exposure bake, development, DI rinse and dry cycle. Program 01_PEB110C90s_MF26A60s PEB 110°C · 90 s Developer MF-26A · 60 s Check Developed openings are clear; no unintended bridges or pinholes. develop	Ring gate Conventional gate Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
P045Inspect contact openingsuvscope□ Done __________	Inspect contact enclosure, alignment and resist clearing at the bottom of the holes. Keep gate-crossing ILD intact. Sample Center, mid-radius and edge; save representative images Check Save site-matched photographs and measured critical dimensions; resolve visible defects before the next irreversible etch/deposition. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P046Etch ILD contact holesCentura-MxP only if RETURN eligible / bound dielectric etcher□ Done __________	Run the bound oxide-contact etch to clear the ILD at source/drain silicon, poly gate tabs and p-type body windows. Account for the different landing heights and preserve silicon/poly after clearing. Reference MXP-OXIDE-ETCH; 700 W; 200 mTorr; Ar/CF₄/CHF₃ 150/15/45 sccm Etch duration CONTACT time from actual ILD thickness and measured rate Overetch limit Less than 10 s overrun after endpoint; 10 s maximum without endpoint monitoring Check Contact bottoms clear with bounded poly/Si loss. Preserve ILD at all metal crossings. PECVD4 use does not establish MxP eligibility; bind the complete route before this visit. contactetch · morph-etch	Ring gate Conventional gate Directional plasma contact etch Directional plasma etching removes exposed horizontal film and produces approximately vertical patterned edges. Lateral bias, selectivity and any sidewall residue remain recipe dependent. Contact walls are steep; this is a plasma opening, unlike the earlier HF oxide clear.
P047Strip contact resist and CFx residueMatrix · RETURN-qualified history after SOD/probing□ Done __________	Remove contact resist and CFx residue with the full O₂ plasma strip. Do not place CFx-contaminated resist directly in communal 1165; any remaining residue uses the specified plasma/EKC265 route. Settings 3.75 Torr; O₂ MFC1 40%; 400 W; 250°C Time 2.5 min starting strip for ~2 µm resist; total ______ min to clear Check Resist is fully cleared, including etch residue. Confirm any additional wet residue clean from the bound route. ash · contactetch	Ring gate Conventional gate Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
P048Inspect the contact bottomsuvscope□ Done __________	Check that S/D, gate and body contacts are open, without residue or excessive undercut. Inspect the poly landings for etch damage. Sample Center, mid-radius and edge; save representative images Check Save site-matched photographs and measured critical dimensions; resolve visible defects before the next irreversible etch/deposition. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Blanket Al–Si and P4 wiring

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
P049Clean contact bottoms and rinseAssigned premetal-clean wet bench□ Done __________	Remove native oxide from the contact bottoms using the lot’s short contact preclean, then rinse. Include ILD loss and opening widening in the etch time. Preclean CONTACT chemistry/time; include ILD thinning and contact enlargement Rinse Complete bound QDR and transfer promptly to drying Check Contact surfaces clear; no excessive ILD loss or exposed-Si recess. wetoxide	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P050Spin-rinse dryDesignated SRD□ Done __________	Move the rinsed wafers to the SRD; complete the full rinse/dry program and transfer in the designated clean cassette. Program 150 mm full rinse/dry Finish No watermarks or visible residue Check Full compatible rinse/dry cycle; no watermarks, residual liquid or backside deposits. cleannonmos	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P051Dehydrate for metal loadingHotplate□ Done __________	Move the dried wafer to the hotplate, then load MRC944 promptly. Bake 120°C · 1 min Check Wafer is water-free before vacuum loading; this short dehydration does not replace the CONTACT preclean. sputter	Ring gate Conventional gate Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
P052Sputter blanket Al–Simrc944□ Done __________	Load the water-free, resist-free wafer. Execute the bound contact sputter clean and target pre-sputter, then deposit Al–Si without a vacuum break. All contacted terminals are temporarily joined by the blanket film. Film / target 500 nm; Al 98% / Si 2% Reference pressure Process base 5×10⁻⁷ Torr; Ar 8 mTorr Power / motion AL current recipe; Al–Si target maximum 3000 W; bound passes/speed Preclean / pre-sputter CONTACT preclean; target pre-sputter at least the bound stabilization time, 1 min reference Check No polymers or tape enter MRC944. Stable deposition and sound film coverage on all contact landings. sputter · morph-deposit	Ring gate Conventional gate Sputter deposition / finite coverage Sputtered metal reaches horizontal surfaces and some sidewalls, with reduced coverage at steep or shadowed edges. Contacts are coated surfaces, not solid filled plugs; continuity requires measurement.
P053Measure the metal witnessalphastep · witness□ Done __________	Measure the metal step on the witness after unloading; record film thickness for the Al etch. Film 500 nm target; measured ______ nm Check Record actual Al–Si thickness for metal etch calibration; no stylus contact on active gate regions. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P054Dehydrate before BARCHotplate□ Done __________	Move the Al-coated wafer to the hotplate before the BARC track. Bake 120°C · 5 min; no HMDS Check No HMDS step is added over aluminum; proceed to BARC using the current coat route. barc	Ring gate Conventional gate Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
P055Coat and cure BARCsvgcoat3□ Done __________	Run the AR3-600 coat, edge-bead removal and cure cycle. Keep the Al covered during the following resist development. BARC AR3-600, approximately 60 nm Historical cure reference 190°C; dwell and track program from AL Check Continuous BARC protects Al from TMAH developer, including critical edges and contact steps. barc · morph-spin	Ring gate Conventional gate Spin coating / cured BARC Spin-coated BARC partly levels the metal topography and is then cured. It can be thinner at convex edges and thicker in recesses; the drawing does not imply a uniform conformal film.
P056Coat Mask 4 resistsvgcoat6□ Done __________	Load the coat track for the no-HMDS MiR-on-BARC cycle. Resist MiR701, 2 µm, no-HMDS BARC-compatible program Historical reference 900 rpm nominal; 90°C, 90 s soft bake Program AL/LITHO no-HMDS variant Check Record the actual recipe and any departure from the bound lot settings. coat · morph-spin	Ring gate Conventional gate Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
P057Expose Mask 4ksaligner · MA8□ Done __________	Align P4 to the contact holes. Pattern separate source, drain, gate and body wiring; route the ring’s center drain over intact ILD. Exposure LITHO dose, intensity/focus and alignment mode for this level Baseline MA8 365/436 nm configuration; exposure time = calibrated dose / measured intensity Check Check mask identity, orientation, tone and overlay before exposure; retain alignment-mark images. aligner	Ring gate Conventional gate Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
P058Develop Mask 4svgdev6□ Done __________	Run the complete post-exposure bake, development, DI rinse and dry cycle. Program 01_PEB110C90s_MF26A60s PEB 110°C · 90 s Developer MF-26A · 60 s Check Developed openings are clear; no unintended bridges or pinholes. develop	Ring gate Conventional gate Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
P059Inspect the metal maskuvscope□ Done __________	Inspect line/space, contact overlap, S/D/G/B separation and the gate crossing. Check for resist bridges and pinholes. Sample Center, mid-radius and edge; save representative images Check Save site-matched photographs and measured critical dimensions; resolve visible defects before the next irreversible etch/deposition. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
P060Harden Mask 4 resistaxcelis□ Done __________	Move to the UV hard-bake tool and run the complete MiR701 thermal/lamp program before etching. Reference MiR701 program U; exact loaded thermal/UV program in LITHO Check Printed edges remain intact; enough resist remains for the following etch. harden	Ring gate Conventional gate Resist hardening The patterned resist is hardened for etching. The mask stays in place; any bake-induced rounding or profile change must remain inside the lithography/etch budget.
P061Open exposed BARCAssigned metal-compatible O₂ plasma tool□ Done __________	Remove BARC only where the metal resist is open, leaving the patterned resist thick enough for the Al etch. BARC opening AL partial-open recipe: power/pressure/O₂/time Film Approximately 60 nm BARC; retain enough resist for the Al etch Check BARC cleared only in intended metal-etch openings; protect the resist pattern and metal under it. barc	Ring gate Conventional gate Patterned plasma BARC opening Plasma clears BARC through the developed resist openings. Actual lateral BARC loss and resist erosion depend on the bound plasma program; the illustration does not assign a calibrated etch slope.
P062Etch and isolate the Al–Si wiringlam7 · 7003 family□ Done __________	Run the metal main etch and interface overetch, then transfer immediately to the corrosion-control strip. Historical main 8 mTorr; TCP/bias 800/100 W; Cl₂/BCl₃ 90/45 sccm Historical overetch 8 mTorr; TCP/bias 700/100 W; Cl₂/BCl₃ 45/60 sccm Actual times AL endpoint/time calibration for measured metal; helium clamp 4 Torr reference Check Metal is isolated through the full thickness; immediately continue to the corrosion-control strip without an inspection queue. metaletch · morph-etch	Ring gate Conventional gate Directional plasma metal etch Directional plasma etching removes exposed horizontal film and produces approximately vertical patterned edges. Lateral bias, selectivity and any sidewall residue remain recipe dependent.
P063Immediately strip resist and BARCMatrix · RETURN-qualified history after SOD/probing□ Done __________	Transfer directly from LAM7 for the Al-compatible post-etch strip; remove resist and BARC without an inspection queue. Settings 3.75 Torr; O₂ MFC1 40%; 400 W; 250°C Time 2.5 min starting strip for ~2 µm resist; total ______ min to clear Check Immediate strip after LAM7; no prolonged atmospheric queue with chlorine-bearing residue. ash	Ring gate Conventional gate Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
P064Complete the Al corrosion-control rinseAssigned metal corrosion-control wet station□ Done __________	Immediately complete the AL corrosion-control rinse/passivation and dry route after the strip. Keep metallized wafers out of MSINK6/MSINK8 piranha. Recipe AL metal-compatible rinse/passivation and drying sequence Check Residual chlorine and strip contamination are removed; no visible attack of Al–Si. metaletch	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P065Inspect the finished metaluvscope□ Done __________	Inspect contact steps, line edges and spaces for stringers, discontinuities and corrosion. Save the final wafer images. Sample Center, mid-radius and edge; save representative images Check Save site-matched photographs and measured critical dimensions; resolve visible defects before the next irreversible etch/deposition. index	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

As-deposited electrical test

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
P066Probe contacts and completed NMOS devicesEB-8□ Done __________	Measure metal continuity/short monitors and contact chains first. Test the candidate body landing separately, then measure rings and conventional devices through their pads. Tie B and S to 0 V only when the body-contact test supports stable body potential under the intended bias. Body contact Two independent body landings: −50 to +50 mV, 1 µA initial compliance; sense body potential under load Transfer VD=50 mV; start VG 0→1→0 V, extend only within TEST after gate-leakage screen; record ID and IG, plus IB if body is tied Device ladder Large ring controls, conventional devices and small pad-accessed devices; ID–VD and junction/field leakage Contact evidence Linear/repeatable contact behavior, chains and geometry-corrected resistance; bare p-Si contact is not presumed ohmic Check Save all as-deposited data. Label each data set body-floating or body-tied; no grounded-body threshold is reported from the floating condition. Record Contacts ___; body-contact result ___; ID–VG/ID–VD/IG/IB ___ probe · contacts · physics	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Visit / destination

Operation, settings and check

Wafer after this visit

P066Probe contacts and completed NMOS devicesEB-8□ Done __________

Measure metal continuity/short monitors and contact chains first. Test the candidate body landing separately, then measure rings and conventional devices through their pads. Tie B and S to 0 V only when the body-contact test supports stable body potential under the intended bias.

Body contact: Two independent body landings: −50 to +50 mV, 1 µA initial compliance; sense body potential under load
Transfer: VD=50 mV; start VG 0→1→0 V, extend only within TEST after gate-leakage screen; record ID and IG, plus IB if body is tied
Device ladder: Large ring controls, conventional devices and small pad-accessed devices; ID–VD and junction/field leakage
Contact evidence: Linear/repeatable contact behavior, chains and geometry-corrected resistance; bare p-Si contact is not presumed ohmic

Check Save all as-deposited data. Label each data set body-floating or body-tied; no grounded-body threshold is reported from the floating condition.

Record Contacts ___; body-contact result ___; ID–VG/ID–VD/IG/IB ___

probe · contacts · physics

Ring gate

Conventional gate

Optional contact-anneal split

EXPERIMENT

Only execute these visits for a selected split with ANNEAL bound. Otherwise the as-deposited test is the final endpoint; mark N/A.

Visit / destination	Operation, settings and check	Wafer after this visit
P067Clean selected wafer for annealingAssigned metal-compatible wet station□ Done __________	Run ANNEAL metal-compatible clean/rinse/dry and transfer in the designated carrier. Retain an unannealed matched control. Clean ANNEAL exact chemistry and rinse/dry Check Selected anneal tool accepts the full SOD/probe/metal history. A wet clean does not automatically restore MOS eligibility. history · sinter	Ring gate Conventional gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
P068Anneal selected contact splitAssigned metal-compatible non-MOS anneal tool□ Done __________	Run the bound contact anneal, including purge, ramp, hold and cool, then unload. Thermal / gas ANNEAL temperature, duration, gas mix and flow Tool boundary Do not substitute a long furnace sinter into RTP3 or use MOS-only Tystar18 by default Check Save temperature trace and final metal condition; no metal damage or unexpected leakage increase. Record Anneal recipe/trace ___ history · sinter	Ring gate Conventional gate Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
P069Repeat electrical measurements after annealEB-8□ Done __________	Repeat the as-deposited contact, body-contact, leakage and transistor measurements using identical sites and timing. Compare with the unannealed control. Comparison Same bias range, illumination and dwell; explicitly record body state Check The contact anneal effect is separated from probe drift or body-state changes; document any degraded structure. Record Matched before/after files ___ probe	Ring gate Conventional gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Visit / destination

Operation, settings and check

Wafer after this visit

P067Clean selected wafer for annealingAssigned metal-compatible wet station□ Done __________

Run ANNEAL metal-compatible clean/rinse/dry and transfer in the designated carrier. Retain an unannealed matched control.

Clean: ANNEAL exact chemistry and rinse/dry

Check Selected anneal tool accepts the full SOD/probe/metal history. A wet clean does not automatically restore MOS eligibility.

history · sinter

Ring gate

Conventional gate

Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.

P068Anneal selected contact splitAssigned metal-compatible non-MOS anneal tool□ Done __________

Run the bound contact anneal, including purge, ramp, hold and cool, then unload.

Thermal / gas: ANNEAL temperature, duration, gas mix and flow
Tool boundary: Do not substitute a long furnace sinter into RTP3 or use MOS-only Tystar18 by default

Check Save temperature trace and final metal condition; no metal damage or unexpected leakage increase.

Record Anneal recipe/trace ___

history · sinter

Ring gate

Conventional gate

Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.

P069Repeat electrical measurements after annealEB-8□ Done __________

Repeat the as-deposited contact, body-contact, leakage and transistor measurements using identical sites and timing. Compare with the unannealed control.

Comparison: Same bias range, illumination and dwell; explicitly record body state

Check The contact anneal effect is separated from probe drift or body-state changes; document any degraded structure.

Record Matched before/after files ___

probe

Ring gate

Conventional gate

Completion criteria

First checkpoint: repeatable ring gate control with low gate leakage, acceptable n+ and poly resistance, and contact-reseat stability. Body state remains floating.
Second checkpoint: M2 preserves the ring controls and isolates conventional gates without attacking existing n+ windows.
Final checkpoint: separate metal-short, contact-chain and gate-leakage tests pass before device extraction. Grounded-body results require a demonstrated body contact, not merely a metal pad.
No field-isolation, lifetime, production-yield or dense-circuit qualification is claimed. These bulk structures teach the modules subsequently used in the SOI tracks.

Process references and source notes

index NanoLab equipment manual index
Equipment index checked 21 September 2026. Critical material-routing, RTP3, CHA, LAM8, MxP, PECVD3/4, MRC944, MSINK6/8 and Tystar18 manual exports were also inspected where used. Coat/develop and remaining recipe blocks retain their earlier-traveler reference basis; exact lot inputs are explicitly bound.
history Materials Control and Compatibility
Manual export inspected 21 September 2026. Material-control codes and tool-specific exceptions govern every return path; cleaning does not automatically erase persistent tool/probe contamination.
cleanmos MSINK6: VLSI MOS Clean
Manual export inspected 21 September 2026: no metal or resist; 120°C piranha, 25:1 HF and 0.1% HCl baths. Applicable bath times and wafer history still follow the current station procedure.
cleannonmos MSINK8: Non-MOS Clean
Piranha reference: 120°C, 10 minutes. Wafer history, dopant residues and probe contact still require the appropriate bath and carrier.
coat SVGCOAT6: photoresist coating
MiR701 2 µm coat/bake reference retained from the prior traveler. This does not qualify its dose on every film stack.
develop SVGDEV6: photoresist development
Reference PEB/develop program retained; bilayer development is separately bound.
aligner Karl Suss MA8 mask aligner
Existing poly traveler exposure route. A calibrated MLA150 transfer can replace it without changing the mask count.
mla MLA150: maskless aligner
Exposure dose, focus and edge placement are measured on the actual stack. Lithography levels are counted independently of exposure-tool choice.
harden Axcelis UV hard bake
MiR701 program U reference for etch masks only, not a lift-off hard bake.
wetoxide MSINK7: acid/base batch processing
Room-temperature oxide opening/strip uses measured rates and the selected chemistry. Tool nomination does not certify acceptance of any new SOD chemistry.
ash Matrix: resist removal
Reference full-strip settings: 3.75 Torr, O₂ MFC1 40%, 400 W, 250°C. A descum is a different, separately calibrated operation.
polyetch LAM8: polysilicon etch
Manual export inspected 21 September 2026. LAM8 is for silicon/poly/SiGe/Ge/SiC, not metal etching or metal masks; 8003 includes oxide breakthrough, main etch and selective overetch. Full post-probe/SOD return eligibility remains part of RETURN.
spin Headway1: manual spinner
Candidate coating platform only; the exact dopant, dispense and waste route are part of binding P-SOD.
sod Filmtronics: spin-on diffusants
Manufacturer product information; it does not establish a diffusion recipe for this gate stack.
rtp RTP3: AccuThermo AW610 Si non-MOS
Manual export inspected 21 September 2026. Non-MOS tool, ≤1100°C, duration constrained by the temperature/time envelope and general 3-minute limit. Exact SOD source-present use and pyrometer/carrier calibration remain lot bindings.
probe Everbeing EB-8 analytical probe station
Electrical measurements here are development screens. Biases are deliberately conservative starting values, not a validated device rating.
pecvd Oxford PECVD3
400 nm SiO₂ is a design target. Deposition rate and film properties are bound by the current chamber recipe.
contactetch Centura MxP oxide etcher
Manual export inspected 21 September 2026. CFx residues require plasma or EKC265 before any communal solvent strip. Overetch has a <10 s endpoint-overrun / 10 s no-endpoint limit; full incoming PECVD/probe/SOD history must be eligible.
sputter MRC944 sputtering with sputter etch
Manual export inspected 21 September 2026: Al–2%Si target maximum 3000 W, no polymers, post-rinse 120°C/1 min dehydration, BARC recommended before TMAH-based lithography. Older 4 kW example settings are not used.
barc SVGCOAT3: LOR and BARC track
Historical AR3-600 BARC and LOR-5A routes. LOR/top-resist edge-bead removal compatibility is part of the lift-off recipe.
metaletch LAM7: aluminum TCP etcher
7003 family reference retained; immediate corrosion-control processing is part of the module.
sinter Tystar18: MOS-clean aluminum sinter
Manual export inspected 21 September 2026: Tystar18 is MOS-only. The optional anneal here uses a separately selected compatible tool; its low-temperature recipe is not transferred to RTP3 as a long hold.
physics Hu: MOS transistor physics
Device-physics background for gate control and body bias; not a recipe qualification.
contacts MIT 6.720J: metal–semiconductor contacts
Contact behavior depends on material and doping. Neither a metal landing nor mechanical chuck contact establishes an ohmic body connection.
pecvd4 Oxford PECVD4: general-purpose oxide deposition
Manual export inspected 21 September 2026. CH4-STD-SiOx Recipe 1010 reference: 350°C, 1000 mTorr, 81 MHz/200 W, Ar/N₂O/N₂/10%-SiH₄-in-Ar 650/150/200/50 sccm, reported rate 171 nm/min. Its Au/Cu-capable contamination environment must be assessed for these active devices.
morph-spin MicroChemicals: spin coating over textured substrates
PDF pp. 1 and 4 explain edge pullback and accumulation in holes/spaces. Direct evidence for resist morphology; analogous leveling shown for SOD is a qualitative liquid-flow inference, not measured coverage for a chosen dopant formulation.
morph-fab Chenming Hu: Device Fabrication Technology, chapter 3
PDF pp. 3–5 and 10–12 support silicon-consuming thermal oxidation, lateral wet-etch retreat and directional plasma etching. The diagrams do not assign calibrated etch angles, undercuts or diffusion lengths.
morph-deposit MEMS Exchange: deposition processes and step coverage
Explains CVD/PVD step-coverage differences and silicon consumption during oxidation. LPCVD wrap, finite PECVD coverage, directional evaporation and reduced PVD sidewall coverage are qualitative morphology conventions.
morph-etch MEMS Exchange: isotropic and anisotropic etching
Distinguishes isotropic lateral undercut, crystallographic wet etching and directional RIE. The mesa route here is directional plasma etching, not a KOH crystal-plane etch.