PROCESS DEVELOPMENT · CLEANROOM TRAVELER

Experimental NMOS · metal gate last

Two lithography levels · phosphorus SOD · evaporated aluminum gate and contacts

This is the fastest bulk-silicon branch for testing gate-controlled conduction without depositing or doping polysilicon. A nominal 109 nm thermal oxide serves as both the gate dielectric and the phosphorus diffusion mask; the second lithography level forms the aluminum gate and source/drain electrodes together by lift-off.

The experiment tests whether oxide survival, dopant blocking, lateral diffusion and aluminum contacts leave a usable two-mask process window. Gate metal stays on oxide and reaches the buried lateral n+ extensions without entering the exposed silicon windows. Large linear devices and ring devices provide a setback ladder and direct silicon access for diagnosis.

This is a development traveler, not a released production process. The strict two-mask wafer has no deliberately formed p-type body contact: initial and final measurements are explicitly floating-body. Optional annealing is a separate split after as-fabricated data have been saved.

Starting wafer: Virgin prime 150 mm p-Si (100), approximately 675 µm; 1–10 Ω·cm baseline, actual lot recorded
Gate / mask oxide: 109 nm nominal dry thermal SiO₂; measure remaining oxide after all strips
Lithography: M1 diffusion windows and marks; M2 aluminum gate and electrodes
Metal: 300 nm evaporated Al baseline; no adhesion metal under the gate
Endpoint: Repeatable gate control, contact/oxide/overlap evidence; body floating

Lot / wafers ____________________Operator ____________________Date ____________________

Step explorer

Listed sequence ↓

1 / 45

Device Section Drag to rotate · scroll to zoom Cut at section

Inspection / measurement

The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

3D process structure

Along channel

Silicon body / handlen+ siliconThermal SiO₂ / BOXPhotoresistLift-off underlayer (LOR)Phosphorus spin-on sourceAluminum metallization

Sections are cut from the same 3D material geometry. Film thickness, etch bias and diffusion lengths are exaggerated; coverage must be verified on the actual wafer.

Geometry and coverage

Diagrams show thermal oxide growing by silicon consumption and wet windows opening by lateral etching. The profile is schematic and vertically exaggerated; actual oxide loss and window boundaries are measured. The center cut shows the gate between source/drain windows; the ring cut crosses source, gate, inner drain, gate and source. A gate-lead corridor must remain oxide-covered in plan view. Blue n+ boundaries and lateral extensions are illustrative. Their shape is not a diffusion calculation or a measured junction profile. No gate metal may cross exposed source/drain silicon. The final body remains floating; the backside oxide and chuck are not an electrical body terminal. The setback ladder is exploratory until the edge-error and useful lateral-diffusion interval in LITHO is supported. Candidate 0.5 / 1 / 2 / 4 µm setbacks are used only where the actual writer/profile resolves them; none is a guaranteed design rule. Morphology is illustrative rather than a dimensional prediction: directional plasma etches have steep walls, wet oxide etches retreat laterally, thermal oxidation consumes silicon, and deposited films follow their stated deposition method. Numerical geometry is deliberately exaggerated for legibility. Spin-on resist, BARC and dopant source films wet accessible relief and partially level it. Convex corners may be thin and recesses thick; a smooth drawing is the intended coverage, not evidence of pinhole-free coating. Wet, baked and thermally converted source states are distinguished.

Incoming wafer and thermal oxide

M001 · Inspect and identify incoming silicon

Inspect the polished face, edge and backside. Load the device wafer and full-wafer oxidation witness into the designated clean cassette; keep reserve wafers separate.

Go to this visit in the run sheet ↓

Lot recipe assignments

Use these assignments wherever their IDs appear in the sequence. Complete the values before starting the affected module.

Assignment	Value for this lot	Context
OX Oxidation	1GATEOXA: 950°C reference; hold ___ min; N₂ anneal ___ °C / ___ min	Set growth time from current dry-oxide monitor data for 109 nm. Record full ramp, anneal and cool recipe.
LITHO Exposure and wet opening	M1 dose/focus ___; M1 oxide etchant/rate ___; M2 dose/focus ___	Record total worst-case edge error e, minimum metal-to-window clearance mS and required useful gate/diffusion overlap mO. For nominal setback s and minimum useful lateral reach xlat: e+mS ≤ s ≤ xlat−e−mO. The interval exists only if xlat ≥ 2e+mS+mO. No lateral reach is inferred from a short RTA.
P-SOD Phosphorus source and thermal cycle	Product/bottle ___; spinner/coat ___; cure ___ °C / ___ min; tool ___; peak ___ °C / ___ s; ambient/ramp/carrier ___	Use one established source-present module. RTP3 is a candidate non-MOS tool, not an assertion of source acceptance. Include both wafer faces in contamination and temperature-sensing setup.
P-STRIP Source removal and oxide budget	Bath ___; rate ___; time ___; post-strip oxide minimum ___ nm; native-oxide preclean ___	Measure source removal and thermal-oxide loss independently. Gate/mask function must survive the entire cycle.
BLOCK Dopant-blocking witness	W-BLOCK: unpatterned oxide-covered witness from the same growth; profile service/method ___; acceptance limit ___	W-BLOCK receives the same phosphorus coat/cure/diffusion/strip. Retain its oxide for depth-resolved SIMS phosphorus profiling into Si against an unprocessed same-lot baseline; specify interface location and contamination/background limit. SIMS measures elemental concentration, so electrical controls still establish channel behavior. Profile analysis is qualification work outside the two-mask device sequence.
RETURN Post-SOD / probe-compatible handling	Wet bench ___; clean ___; SRD/carrier ___; accepted return tools ___	After RTP3 or probe-tip contact, retain non-MOS/probe history. No automatic return to MSINK6 or MOS furnaces. Probe separate witnesses when the device-wafer return path is not established.
LIFT Lift-off bilayer	LOR-5A thickness ___ / bake ___; MiR701 top coat 2 µm target / bake ___; developer ___ / time ___; solvent ___ / ___ °C	Undercut and discontinuity must suit 300 nm Al. Native/contact oxide is retained until the final premetal clean; quantify exposed-Si developer attack on a matching witness.
AL CHA contact clean and evaporation	Base pressure ___; CHA ion-clean controls 100 V / 2 A reference, duration ___ s; Al rate ___ nm/s; 300 nm target	Record the actual tool field units; 100 V / 2 A are not a measured wafer ion-energy/current-density dose. Ion cleaning also strikes gate oxide. Bound contact clearing, oxide loss and leakage on witnesses.
TEST Electrical limits	Gate maximum ___ V; gate-current release criterion ___; current ranges ___; dwell 1 s starting	Set the maximum from the surviving dielectric and measured leakage; geometric oxide thickness alone is not a reliability rating.
ANNEAL Optional contact-anneal split	N/A unless selected: tool ___; ___ °C / ___ min; gas ___; clean/return route ___	As-fabricated measurements come first. Tystar18 is not automatically eligible after non-MOS RTP/CHA/lift-off/probe history. A wafer entering MSINK16/18 must not later enter MSINK1/6/7/8; use a compatible clean route.

Cleanroom sequence

45 visits

Each numbered visit follows the wafer to a tool, bench or measurement station. The section at right shows the intended structure after that visit.

Silicon body / handlen+ siliconThermal SiO₂ / BOXPhotoresistLift-off underlayer (LOR)Phosphorus spin-on sourceAluminum metallization

Incoming wafer and thermal oxide

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
M001Inspect and identify incoming siliconuvscope□ Done __________	Inspect the polished face, edge and backside. Load the device wafer and full-wafer oxidation witness into the designated clean cassette; keep reserve wafers separate. Wafer 150 mm p-Si (100), approximately 675 µm Lot Record measured/supplier resistivity, face finish and backside state Check No cracks, gross particles, tape or resist residue. Wafer identity follows every transfer. Record Wafer ID ___; lot/resistivity ___; initial photographs ___ index	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M002Clean virgin siliconMSINK6□ Done __________	Run the virgin-wafer MOS-clean sequence; complete each bath and rinse in order. Sequence Piranha → QDR → dilute HF → QDR → dilute HCl → QDR → dilute HF → QDR Historical reference Piranha 120°C, 1–5 min; HF 25:1, room temperature, 1 min each; HCl 0.1%, room temperature, 1 min Rinse QDR endpoint >10 MΩ·cm Check Use the current bath program; the virgin-wafer route applies only to the documented incoming history. cleanmos · history	Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
M003Spin-rinse dry for oxidationMSINK6 SRD□ Done __________	Transfer the rinsed cassette to the compatible spin-rinse dryer; run the complete rinse/dry cycle and move promptly in the clean carrier to the furnace. Cycle 150 mm full rinse/dry; historical rinse endpoint >12 MΩ·cm Check No watermarks; preserve the clean-to-load queue record. Record Clean completed ___; furnace loaded ___ cleanmos	Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
M004Grow gate / diffusion-mask oxideTystar1□ Done __________	Load device and witness wafers. Execute the complete purge, insertion, dry oxidation, N₂ anneal and controlled cooling program in binding OX. Target 109 nm dry thermal SiO₂ on both faces Reference recipe 1GATEOXA; 950°C, dry O₂ 9000 sccm Anneal N₂ 9000 sccm reference; time/temperature from OX Check Save the full recipe/temperature trace. Do not substitute growth time from nominal literature rates. Record Recipe ___; oxidation hold ___; run trace ___ oxide · morph-fab	Along channel Thermal oxidation / silicon consumption Thermal oxide consumes silicon at the front and back surfaces and expands outward. It is grown from Si, not deposited as a cap; the silicon/oxide boundary movement is exaggerated for visibility.
M005Cool and unload oxidation boatTystar1 cooling rack□ Done __________	Complete the trained purge/unload/cooling sequence, restore standby, and unload cool wafers into the clean cassette. Transfer Clean quartz rack and designated carrier; no uncontrolled contact with the polished face Check Inspect for handling damage; separate the metrology witness without contaminating clean reserves. oxide	Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
M006Map thermal oxideellips2 / nanoduv□ Done __________	Measure the oxide-only device and witness stacks using the thermal SiO₂/Si optical model. Map Center plus four radial sites; larger map where available Nominal 109 nm; record actual mean and range Check Fit quality and spatial variation support the intended starting oxide. Retain the measurement coordinates for post-strip comparison. Record tOX mean ___ nm; min/max ___; map ___ index	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

M1 · diffusion windows and alignment marks

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
M007Clean oxide surfaceHistory-compatible oxide-preserving wet bench□ Done __________	Remove handling contamination with the selected oxide-preserving clean, then complete its rinse sequence. Retain the thermal oxide on both faces. Clean Pre-SOD bench/chemistry from RETURN; do not insert an unbudgeted HF dip Check No organic film, watermark or avoidable oxide loss. cleannonmos · history	Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
M008Dry after oxide cleanDesignated SRD□ Done __________	Complete the full rinse/dry program and transfer the dry wafer to the resist track. Cycle 150 mm full rinse/dry Check Dry front/back surfaces and particle-free carrier. index	Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
M009Coat and soft-bake M1SVGCOAT6□ Done __________	Run the complete HMDS, resist coat, edge/backside clean and soft-bake program. Resist MiR701, 2 µm Historical reference HMDS module 100°C; final spin 900 rpm; soft bake 90°C, 90 s Program 01_MiR701_2.0um_Bake90C90s Check Continuous resist at oxide edges and acceptable edge-bead removal. coat · morph-spin	Along channel Spin coating / baked resist The spin-coated film wets the relief and partly smooths its topography: convex corners may be thinner and recesses thicker. This visit ends after the specified bake; the drawing shows a solid, partly planarized coat, not a uniform shell.
M010Expose M1 diffusion patternMLA150□ Done __________	Load the prepared DIFF pattern with the recorded wafer orientation and expose the silicon-window openings and alignment marks. Exposure M1 dose/focus/write mode from LITHO Tone Positive resist: expose intended oxide openings Check Pattern origin, scale and tone agree with the lot drawing; preserve the ring gate-lead oxide corridor. mla	Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
M011Develop M1SVGDEV6□ Done __________	Run the PEB, developer, DI rinse and dry program. Historical reference 01_PEB110C90s_MF26A60s; PEB 110°C, 90 s; MF-26A, 60 s Check Cleared resist in diffusion windows; no residual scum. develop	Along channel Resist development Development opens the exposed resist while leaving the mask over retained material. Wall slope and bottom clearing depend on dose, bake and developer; the drawn profile is the intended result.
M012Inspect M1uvscope□ Done __________	Inspect window edges, oxide channel webs, ring corridor and alignment marks at center and radial sites. Record Printed opening dimensions and representative images Check No resist bridges, broken oxide-protection features or pinholes over the channel. index	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M013Harden the M1 etch maskAxcelis□ Done __________	Run the selected MiR701 UV/thermal hard-bake program for wet-etch resistance. Reference MiR701 program U; use the lot-loaded program Check This hardening applies to M1 only; preserve its printed edges. harden	Along channel Resist hardening The patterned resist is hardened for etching. The mask stays in place; any bake-induced rounding or profile change must remain inside the lithography/etch budget.
M014Open oxide diffusion windowsMSINK7 / assigned oxide-etch station□ Done __________	Etch exposed thermal oxide with the bath in LITHO; preserve channel webs and ring corridor. Transfer immediately through the full QDR. Clear time Measured oxide thickness / measured thermal-oxide rate + specified clear margin Temperature Room-temperature bath unless LITHO specifies otherwise Historical rinse MSINK7 complete QDR: four fill/dump cycles Check Complete window clearing with bounded lateral undercut; all oxide loss is entered in the thickness budget. Record Bath/rate ___; etch time ___; oxide loss ___ wetoxide · morph-etch	Along channel Isotropic wet oxide etch Wet oxide etching opens the diffusion windows and retreats laterally beneath the resist edge. The resulting exposed-silicon boundary, rather than the drawn mask edge, sets the later metal-gate clearance.
M015Dry the opened waferDesignated SRD□ Done __________	Run the full rinse/dry cycle after the oxide etch. Transfer Keep the resist mask intact until the strip visit Check No retained rinse water or salt residue. index	Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
M016Strip M1 resistMatrix□ Done __________	Run a complete resist strip; remove hardened resist before the source preparation clean. Historical full-strip reference 3.75 Torr; O₂ MFC1 40%; 400 W; 250°C Starting duration 2.5 min for approximately 2 µm resist; final duration from clearing evidence Check Full resist removal. The ash may grow a thin surface oxide on exposed silicon. ash	Along channel Resist removal The sacrificial resist mask is removed, exposing the completed film profile. The drawing assumes the specified residue check passes; it does not erase underlying etch undercut or film loss.
M017Measure final diffusion-window geometryuvscope□ Done __________	Inspect and measure the etched opening edges, channel oxide webs and ring corridor; retain the edge locations needed to evaluate M2 setback. Sampling Center plus four radial positions; all setback families represented Check No unintended connection between inner drain and outer source; record etch bias independently of lithography bias. Record Final opening CDs ___; oxide undercut estimate ___ index	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Phosphorus SOD and post-diffusion witnesses

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
M018Prepare silicon for the source filmAssigned SOD preclean wet bench□ Done __________	Complete the source-compatible organic/ionic clean and any brief native-oxide removal specified in P-STRIP; rinse completely. Surface preparation Use exact P-SOD/P-STRIP chemistry; budget loss from the gate oxide and both window edges Check Exposed silicon is ready for the selected source chemistry without exhausting the oxide-mask budget. wetoxide · sod · history	Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
M019Dry and transfer to source coatingDesignated SOD-compatible dryer□ Done __________	Run the selected rinse/dry sequence; transfer promptly to the source spinner in the designated carrier. Queue Record dry-to-coat time Check No watermarks or uncontrolled delay; witnesses use the same preparation. history	Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
M020Spin phosphorus dopantHeadway1 or assigned SOD spinner□ Done __________	Coat the device wafer and matched witnesses using P-SOD; maintain the selected edge and backside exclusion. Source Product/bottle and age from P-SOD Coat Dispense, rpm, duration and film target from P-SOD Check Continuous source film without cracks, streaks or contamination of excluded wafer surfaces. Record Bottle ___; coat cycle ___; witness thickness ___ spin · sod · morph-spin	Along channel Spin coating / wet dopant source The wet spin-on source reaches accessible tops and sidewalls and can gather at low corners. Its partly leveled profile is illustrative; actual wetting and corner thickness depend on the selected formulation.
M021Cure source filmAssigned exhausted hotplate / oven□ Done __________	Execute the exact product cure and controlled cool; use the source-compatible carrier for thermal loading. Cure P-SOD temperature, time and ambient Check Source dry/cured to the specified state, not visibly cracked or flaking. sod	Along channel Source cure / dry precursor The cure removes solvent and converts the wet source into the specified dry precursor. Some shrinkage and profile change are expected; the retained coating is not a second deposited layer.
M022Diffuse phosphorusRTP3 candidate / assigned source-present thermal tool□ Done __________	Load the wafer and witnesses; execute the complete purge, ramp, hold and cool cycle in P-SOD. Preserve actual temperature and gas traces. Peak / hold P-SOD: ___ °C / ___ s Sensing Calibration for oxide-coated backside, selected carrier and pyrometer setup History RTP3 use establishes a non-MOS history for subsequent processing RTP3 envelope ≤1100°C; duration limited by the current temperature/time curve and general 3-minute maximum. A longer furnace diffusion is a different bound thermal route. Check Cycle trace matches its recipe. No inference of lateral junction reach is made from the schematic. Record Recipe/trace ___; carrier ___; run deviations ___ rtp · history · morph-fab	Along channel Thermal diffusion / lateral spread Dopant enters exposed silicon in contact with the source and spreads laterally as well as inward. The remaining source is converted glass; colored silicon is a qualitative doped volume, not a concentration contour. Useful lateral n+ reach beneath the oxide must be measured before selecting a gate setback. Phosphorus enters exposed silicon and diffuses laterally beneath the oxide edge; the drawn reach is illustrative.
M023Inspect cooled source-coated waferuvscope□ Done __________	After thermal-tool cooling/unload, inspect the source glass, front/back particles and gross film damage using the compatible carrier. Record Before-strip images at monitor and device locations Check No source loss, wafer fracture or unexpected backside deposits. index · history	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M024Remove source glassAssigned P-STRIP wet bench□ Done __________	Strip the phosphorus-containing source and interfacial residue using the witnessed P-STRIP endpoint; immediately complete the rinse sequence. Etch P-STRIP chemistry, time and actual bath temperature Oxide accounting Include both source-strip and native-oxide-removal losses Check Source is removed while a continuous channel dielectric remains; use the accepted dopant-waste route. wetoxide · sod · history · morph-fab	Along channel Source-glass removal The source glass is removed while the doped silicon remains. Accessible gate-edge oxide and masking oxide may also recede according to the source-specific strip; the final loss requires measurement.
M025Dry after source removalDesignated post-SOD dryer□ Done __________	Complete the compatible rinse/dry program and transfer in the non-MOS carrier. Routing RETURN applies from this point; no MOS-clean reset is assumed Check No residue or watermarks. history	Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
M026Map surviving oxideellips2 / nanoduv□ Done __________	Measure the same oxide-covered witness sites measured before diffusion. Inspect the channel-window edges with the metrology microscope. Measurements Remaining oxide mean/minimum and fit quality Comparison Before vs after SOD/strip at matching coordinates Check P-STRIP oxide minimum is met; thickness evidence is supplemented by subsequent electrical leakage tests. Record Post-strip mean ___ nm; minimum ___ nm; loss ___ nm index	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M027Measure exposed n+ sheet resistanceCDE ResMap · witness only□ Done __________	Measure the bare-Si witness or designated large n+ patch using the correct geometry correction. Keep sharp tips away from device gate oxide. Record Sheet resistance and site-to-site variation; measurement-current setting Check Do not infer gate control or masked-region blocking from n+ resistance alone. Record n+ Rs ___ Ω/□; map ___ index	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M028Measure diffusion and contact-control structuresEB-8 · sacrificial witness / designated test die□ Done __________	Probe the gap ladder and source-window replicas at low bias. Record surface condition, probe locations, leakage and resistance for comparison after metal. Start Two-terminal ±50 mV; 1–10 µA compliance; actual current ranges saved Controls Gap/no-gate replicas; W-BLOCK remains unprobed for the explicitly bound depth-profile method. Check Avoid consuming device-wafer clean eligibility: probe a witness unless the RETURN path explicitly covers the device wafer. Record Probe map ___; gap data ___; witness ID ___ probe · history	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M029Transfer dopant-blocking witness for profilingClean sample-transfer station · witness only□ Done __________	Package the designated W-BLOCK witness and an unprocessed same-lot baseline in the profile-service carrier. Transfer them to the analysis route in BLOCK while device wafers remain in their process carrier. Measurement Depth-resolved phosphorus profile across the surviving oxide into silicon; BLOCK service/method and acceptance limit Device flow This witness exits the device traveler; no extra device lithography level is added Check Witness identity, full thermal/strip history and measured remaining oxide accompany the sample. No production masking claim is made before the profile/electrical evidence exists. Record Witness IDs ___; transfer/profile record ___ sod	Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.

M2 · aluminum gate and source/drain lift-off

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
M030Clean before the lift-off bilayerAssigned post-SOD / post-probe wet bench□ Done __________	Use RETURN to remove organic handling contamination while preserving the channel dielectric. Retain contact-surface oxide until the final in-vacuum contact clean. Recipe RETURN oxide-preserving clean and complete rinse Surface check Exposed-silicon developer compatibility is established on the LIFT witness Check No automatic MSINK6 return. A native oxide film is not assumed to guarantee protection from developer attack. history · solvent	Along channel Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
M031Dry for bilayer coatingDesignated post-SOD dryer□ Done __________	Complete the compatible rinse/dry program and transfer to the bilayer coat route. Queue Dry-to-coat time recorded Check No watermarks or particles. history	Along channel Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
M032Coat and bake LOR underlayerSVGCOAT3 / assigned bilayer coat tool□ Done __________	Apply LOR-5A and run its complete bake/cool cycle from LIFT. Film / bake LIFT thickness, spin, bake temperature/time Profile target Undercut supports discontinuous deposition of 300 nm Al Check Uniform underlayer and edge condition; no HMDS or solvent substitution beyond the bilayer recipe. barc · lor · morph-spin	Along channel Spin coating / baked LOR The liquid LOR underlayer partly smooths surface relief, then is baked. It is the lower sacrificial layer of the later lift-off profile; no undercut exists until development.
M033Coat and bake imaging resistAssigned LOR-compatible coat tool□ Done __________	Coat the MiR701 imaging layer, then complete its soft bake and cool. Use the bilayer-compatible edge/backside clean. Top resist 2 µm target; spin and bake from LIFT Edge solvent Do not substitute the standard SVGCOAT6 EBR without demonstrated LOR compatibility Check No dissolution of the LOR underlayer or exposed backside residue. coat · barc · lor · morph-spin	Along channel Spin coating / baked imaging resist Imaging resist is spun and baked above LOR. Both coatings partially level the relief; the two distinct layers are retained until the metal pattern is developed.
M034Align and expose M2 metal footprintsMLA150□ Done __________	Align to M1 marks; expose the aluminum gate, source/drain pads and gate lead. Keep the ring center drain inside the ring. Dose/focus M2 settings from LITHO Tone Positive lift-off: expose where metal is to remain Geometry Use the prescribed gate setback ladder relative to the final oxide-window edge Check Gate footprint remains entirely on oxide; routing does not cross bare source/drain silicon. mla	Along channel Lithographic exposure Exposure changes the resist chemistry, not the film geometry. Physical openings appear at the subsequent development visit.
M035Develop the lift-off openingsAssigned bilayer developer□ Done __________	Execute LIFT PEB/develop, rinse and dry, clearing both imaging resist and LOR in the metal openings. Recipe LIFT developer, temperature, time and agitation mode No hard bake Preserve the soluble undercut profile for lift-off Check No polymer scum in contacts or under the gate; quantify any exposed-Si loss on the matched witness. develop · barc · lor · morph-etch	Along channel Bilayer development / LOR undercut Development opens both films and recesses LOR laterally beneath the upper resist. This re-entrant profile must keep later evaporated Al on the resist roof disconnected from Al in the openings.
M036Inspect metal placement and undercutuvscope / profile witness□ Done __________	Measure gate-to-window edge placement and compare with the setback ladder. Inspect the developed witness profile and the source/drain openings. Record Placement error, undercut/profile and gate continuity Gate geometry Actual final oxide edge is the reference, not the CAD edge Check No gate-over-window short geometry; no collapsed/bridged lift-off profile. Record Overlay ___; setback family ___; profile image ___ index	Along channel Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M037Clean contacts and evaporate aluminumCHA□ Done __________	Load the wafer and contact/oxide/thickness witnesses in the normal-facing lift-off holder. Pump, apply the bounded AL ion-clean dose, condition the Al source with shutter closed, deposit, cool, vent and unload without a vacuum break between clean and deposition. Metal Al 300 nm nominal; source/tooling factor from AL Contact clean CHA controls 100 V / 2 A reference; AL duration and actual settings. Exposed gate oxide receives the same clean. Deposition AL vacuum/rate limits; preserve lift-off resist temperature/profile Check Stable rate, no source spitting, adequate contact clearing and acceptable witness oxide loss. No adhesion metal is silently added under the gate. Record Base pressure ___; ion dose ___; rate ___; thickness ___ cha · morph-deposit	Conventional gate Ring gate Directional evaporation / lift-off profile Al arrives predominantly along the evaporator source line of sight. The LOR undercut separates metal on the resist roof from metal in the openings; shadowed walls receive less coating, not a uniform Al shell. Aluminum coats the opened device footprints and the resist top. The unwanted top film is removed at lift-off.
M038Lift off unwanted aluminumMSINK16/18 · dedicated metal-compatible solvent bath□ Done __________	Soak in the LIFT remover, exchange clean solvent gently and lift the resist/overlying Al. Keep removed flakes from redepositing on the wafer. Solvent Microposit Remover 1165 candidate; product/temperature/time from LIFT Mechanical action Begin with soak/fluid exchange; no uncontrolled ultrasound Check Complete lift-off without tearing narrow gates or leaving fences. MSINK16/18 history excludes later MSINK1/6/7/8 use; retain this history in the final/anneal carrier record. solvent · lor · morph-deposit	Conventional gate Ring gate Lift-off / remove sacrificial bilayer Dissolving the LOR/resist removes the Al carried on top of it. Gate and S/D metal remain only in the developed openings; their separation requires the undercut and clean lift-off shown in the previous step.
M039Rinse and dry after lift-offAssigned metal-compatible solvent rinse / dry station□ Done __________	Complete the LIFT solvent-rinse and dry sequence using fresh compatible solvent and the designated drying method. Sequence Exact rinse/dry route from LIFT; avoid residue-forming solvent substitutions Check No solvent stain, retained flakes or wet residue on the pads. solvent	Conventional gate Ring gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
M040Inspect finished gate and electrodesuvscope□ Done __________	Inspect gate continuity, oxide-window clearances, source/drain gaps, lift-off fences and the ring gate-lead corridor. Sampling Every setback family and at least three device replicas Also inspect Bare n+ access patches retained beside metal for contact comparisons Check No metal bridges, cracked gate lines or visible corrosion. Save final images before probing. Record Final inspection images ___ index	Conventional gate Ring gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.
M041Measure aluminum thicknessAlpha-Step · witness□ Done __________	Measure the metal step on the evaporation witness without scratching active device gate regions. Target 300 nm; actual step height and variation recorded Check Film thickness is compatible with the observed lift-off profile and continuity. Record Al thickness ___ nm index	Conventional gate Ring gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

As-fabricated electrical test

EXPERIMENT

Visit / destination	Operation, settings and check	Wafer after this visit
M042Measure as-fabricated contacts and NMOS behaviorEB-8□ Done __________	Verify SMU-to-tip mapping on a known resistor; connect device G/S/D with the chuck electrically isolated. Compare metal contacts with direct n+ access and screen persistent G–S/G–D conduction before full transfer sweeps. Measure ID–VG on at least three replicas per selected setback. Reseat contacts and repeat forward/reverse sweeps, with fixed illumination and timing. Compare no-gate controls and low-bias ID–VD at several gate settings. Contacts Start ±50 mV; 1–10 µA current compliance Gate screen S and D at 0 V; VG 0→1→0 V; 10 nA gate-current compliance initially Settling 1 s/point starting; distinguish displacement current from steady leakage Initial transfer S=0 V; VD=50 mV; VG 0→1→0 V; 25–50 mV steps Range extension 2 / 3.3 / 5 V only after leakage screening and within TEST maximum Current limits Initial ID 10 µA; increase as required after screening and mark all compliance hits Body Floating throughout; no top-side p-body contact exists Check Body is floating. Compliance-limited points are flagged and are not treated as device transfer data. Repeatable modulation survives reseating and sweep-direction changes. Distinguish short, contact limitation and underlap from transistor behavior. Record As-fabricated contacts / IG / ID–VG / ID–VD ___; probe/device map ___; chosen setback ___ probe · contacts · physics	Conventional gate Ring gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Visit / destination

Operation, settings and check

Wafer after this visit

M042Measure as-fabricated contacts and NMOS behaviorEB-8□ Done __________

Verify SMU-to-tip mapping on a known resistor; connect device G/S/D with the chuck electrically isolated. Compare metal contacts with direct n+ access and screen persistent G–S/G–D conduction before full transfer sweeps. Measure ID–VG on at least three replicas per selected setback. Reseat contacts and repeat forward/reverse sweeps, with fixed illumination and timing. Compare no-gate controls and low-bias ID–VD at several gate settings.

Contacts: Start ±50 mV; 1–10 µA current compliance
Gate screen: S and D at 0 V; VG 0→1→0 V; 10 nA gate-current compliance initially
Settling: 1 s/point starting; distinguish displacement current from steady leakage
Initial transfer: S=0 V; VD=50 mV; VG 0→1→0 V; 25–50 mV steps
Range extension: 2 / 3.3 / 5 V only after leakage screening and within TEST maximum
Current limits: Initial ID 10 µA; increase as required after screening and mark all compliance hits
Body: Floating throughout; no top-side p-body contact exists

Check Body is floating. Compliance-limited points are flagged and are not treated as device transfer data. Repeatable modulation survives reseating and sweep-direction changes. Distinguish short, contact limitation and underlap from transistor behavior.

Record As-fabricated contacts / IG / ID–VG / ID–VD ___; probe/device map ___; chosen setback ___

probe · contacts · physics

Conventional gate

Ring gate

Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Optional contact-anneal split

EXPERIMENT

Execute only when ANNEAL is filled for a selected split. Otherwise the preceding as-fabricated test is the endpoint; mark these visits N/A.

Visit / destination	Operation, settings and check	Wafer after this visit
M043Clean the selected anneal splitAssigned metal-compatible clean station□ Done __________	Run only the ANNEAL clean/rinse/dry sequence for the selected wafer or witness. Do not choose MSINK1/6/7/8 after MSINK16/18. Recipe ANNEAL clean and transfer route Preserve control Retain an unannealed matched device or wafer Check As-fabricated files are saved and the selected tool accepts the entire history. history · sinter	Conventional gate Ring gate Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.
M044Anneal the selected splitAssigned non-MOS metal-compatible anneal tool□ Done __________	Run the ANNEAL purge, ramp, hold and cool program; unload in the designated carrier. Peak / hold / gas ANNEAL values; no generic aluminum-sinter recipe is implied Check No automatic use of MOS-clean Tystar18. Record changes in metal appearance and contact behavior. Record Anneal run trace ___ history · sinter	Conventional gate Ring gate Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.
M045Remeasure the annealed splitEB-8□ Done __________	Repeat the same contact, leakage, transfer and output measurements with identical sites, bias limits, illumination and dwell. Comparison Before/after anneal; same body-floating condition Check Annealing improves or preserves the measured quantities; it does not establish production reliability. Record Matched before/after data ___ probe	Conventional gate Ring gate Inspection / measurement The section shows the structure being inspected or measured. This visit does not create the profile; actual dimensions and continuity come from the recorded witness or electrical result.

Visit / destination

Operation, settings and check

Wafer after this visit

M043Clean the selected anneal splitAssigned metal-compatible clean station□ Done __________

Run only the ANNEAL clean/rinse/dry sequence for the selected wafer or witness. Do not choose MSINK1/6/7/8 after MSINK16/18.

Recipe: ANNEAL clean and transfer route
Preserve control: Retain an unannealed matched device or wafer

Check As-fabricated files are saved and the selected tool accepts the entire history.

history · sinter

Conventional gate

Ring gate

Clean / surface preparation The drawing preserves the structural stack at this scale. Native oxide, residue and any film loss remain governed by the specified chemistry and measured loss budget.

M044Anneal the selected splitAssigned non-MOS metal-compatible anneal tool□ Done __________

Run the ANNEAL purge, ramp, hold and cool program; unload in the designated carrier.

Peak / hold / gas: ANNEAL values; no generic aluminum-sinter recipe is implied

Check No automatic use of MOS-clean Tystar18. Record changes in metal appearance and contact behavior.

Record Anneal run trace ___

history · sinter

Conventional gate

Ring gate

Transfer / unchanged structure No new structural layer is drawn at this visit; the material stack carries forward from the preceding step.

M045Remeasure the annealed splitEB-8□ Done __________

Repeat the same contact, leakage, transfer and output measurements with identical sites, bias limits, illumination and dwell.

Comparison: Before/after anneal; same body-floating condition

Check Annealing improves or preserves the measured quantities; it does not establish production reliability.

Record Matched before/after data ___

probe

Conventional gate

Ring gate

Completion criteria

At least three replicas show repeatable ID modulation with gate bias; repeat sweeps, reseating and no-gate controls distinguish transistor action from contact drift.
Gate current, oxide survival and masked witness data support dielectric integrity and phosphorus blocking; thickness alone is insufficient.
The setback ladder identifies an actual interval with neither gate-to-S/D short nor excessive underlap resistance. Large channel length does not solve an access gap.
Contact resistance and n+ sheet resistance are measured independently. Early floating-body curves do not establish controlled-body threshold, device reliability, production yield or lifetime.

Process references and source notes

index NanoLab equipment manual index
Equipment index checked 21 September 2026. Critical material-routing, RTP3, CHA, LAM8, MxP, PECVD3/4, MRC944, MSINK6/8 and Tystar18 manual exports were also inspected where used. Coat/develop and remaining recipe blocks retain their earlier-traveler reference basis; exact lot inputs are explicitly bound.
history Materials Control and Compatibility
Manual export inspected 21 September 2026. Material-control codes and tool-specific exceptions govern every return path; cleaning does not automatically erase persistent tool/probe contamination.
cleanmos MSINK6: VLSI MOS Clean
Manual export inspected 21 September 2026: no metal or resist; 120°C piranha, 25:1 HF and 0.1% HCl baths. Applicable bath times and wafer history still follow the current station procedure.
cleannonmos MSINK8: Non-MOS Clean
Piranha reference: 120°C, 10 minutes. Wafer history, dopant residues and probe contact still require the appropriate bath and carrier.
oxide Tystar1: MOS Gate Oxidation
1GATEOXA reference starting settings retained from the prior traveler; growth time and anneal inputs depend on the current monitor calibration.
coat SVGCOAT6: photoresist coating
MiR701 2 µm coat/bake reference retained from the prior traveler. This does not qualify its dose on every film stack.
develop SVGDEV6: photoresist development
Reference PEB/develop program retained; bilayer development is separately bound.
mla MLA150: maskless aligner
Exposure dose, focus and edge placement are measured on the actual stack. Lithography levels are counted independently of exposure-tool choice.
harden Axcelis UV hard bake
MiR701 program U reference for etch masks only, not a lift-off hard bake.
wetoxide MSINK7: acid/base batch processing
Room-temperature oxide opening/strip uses measured rates and the selected chemistry. Tool nomination does not certify acceptance of any new SOD chemistry.
ash Matrix: resist removal
Reference full-strip settings: 3.75 Torr, O₂ MFC1 40%, 400 W, 250°C. A descum is a different, separately calibrated operation.
spin Headway1: manual spinner
Candidate coating platform only; the exact dopant, dispense and waste route are part of binding P-SOD.
sod Filmtronics: spin-on diffusants
Manufacturer product information; it does not establish a diffusion recipe for this gate stack.
rtp RTP3: AccuThermo AW610 Si non-MOS
Manual export inspected 21 September 2026. Non-MOS tool, ≤1100°C, duration constrained by the temperature/time envelope and general 3-minute limit. Exact SOD source-present use and pyrometer/carrier calibration remain lot bindings.
probe Everbeing EB-8 analytical probe station
Electrical measurements here are development screens. Biases are deliberately conservative starting values, not a validated device rating.
barc SVGCOAT3: LOR and BARC track
Historical AR3-600 BARC and LOR-5A routes. LOR/top-resist edge-bead removal compatibility is part of the lift-off recipe.
cha CHA e-beam evaporator and ion clean
Manual export inspected 21 September 2026: soft-baked i/g/DUV-LOR lift-off stacks supported; ion-mill tool controls 100 V / 2 A, duration recipe-dependent and very low contact-cleaning rate. Neither ion energy nor removed oxide thickness is inferred from those control values.
lor Kayaku LOR/PMGI lift-off resists
Bilayer profile and bake/develop selection must be compatible with the selected metal thickness and underlying silicon.
solvent MSINK16/18: general-purpose processing
Metal-compatible dedicated lift-off bath; solvent product, temperature and waste route are bound for the lot.
sinter Tystar18: MOS-clean aluminum sinter
Manual export inspected 21 September 2026: Tystar18 is MOS-only. The optional anneal here uses a separately selected compatible tool; its low-temperature recipe is not transferred to RTP3 as a long hold.
physics Hu: MOS transistor physics
Device-physics background for gate control and body bias; not a recipe qualification.
contacts MIT 6.720J: metal–semiconductor contacts
Contact behavior depends on material and doping. Neither a metal landing nor mechanical chuck contact establishes an ohmic body connection.
morph-spin MicroChemicals: spin coating over textured substrates
PDF pp. 1 and 4 explain edge pullback and accumulation in holes/spaces. Direct evidence for resist morphology; analogous leveling shown for SOD is a qualitative liquid-flow inference, not measured coverage for a chosen dopant formulation.
morph-fab Chenming Hu: Device Fabrication Technology, chapter 3
PDF pp. 3–5 and 10–12 support silicon-consuming thermal oxidation, lateral wet-etch retreat and directional plasma etching. The diagrams do not assign calibrated etch angles, undercuts or diffusion lengths.
morph-deposit MEMS Exchange: deposition processes and step coverage
Explains CVD/PVD step-coverage differences and silicon consumption during oxidation. LPCVD wrap, finite PECVD coverage, directional evaporation and reduced PVD sidewall coverage are qualitative morphology conventions.
morph-etch MEMS Exchange: isotropic and anisotropic etching
Distinguishes isotropic lateral undercut, crystallographic wet etching and directional RIE. The mesa route here is directional plasma etching, not a KOH crystal-plane etch.